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FPGA technical questions

2021 November 13

Hi. Why is ISE telling me that this is an illegal operation with a real number? SAMPLE_SIZE is an integer parameter. I also tried it without $floor and with 2 instead of 2.0, but I'm getting the same error on this line.

It compiled fine in iverilog.

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16:56пожаловаться #1

2021 November 14

Konstantin in FPGA technical questions

It's a part of verilog 2005 standard, and ISE probably uses some older version

out of curiousity, do you have specific reason to use ISE instead of Vivado?

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00:46пожаловаться #2

Konstantin in FPGA technical questions

here are some notes about it
https://support.xilinx.com/s/question/0D52E00006hpYzASAU/complete-list-of-verilog-system-functions-and-tasks?language=en_US
I would suggest you to install Vivado and compile everything as a SystemVerilog

Xilinx

Complete list of Verilog system functions and tasks

Does anyone know of a compelte list of Verliog System functions and tasks?

I know the ISim manual (UG660) has a list of supported system functions in appendix a, but some system functions that work for me are not in the list. (The XST user guide - UG687 doesn't seem to list available system functions).

Things like $ceil, $floor, $ln seem to work but they aren't listed.
I'd love to get a full list of such functions - they can be incredibly useful!

For example, the following will simulate correctly

integer j;initialbegin j = $ln(8)/$ln(2);end

These Systems functions also work in ModelSIM, but again, the ModelSim doco does not mention the existance of these functions.

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00:48пожаловаться #3

Foxner in FPGA technical questions

What is part of the 2005 standard?

Anyway, I solved it by using $rtoi(). I guess if I wanted the result rounded I'd have to use $rtoi(x + 0.5).

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00:48пожаловаться #4

Foxner in FPGA technical questions

Yes, Vivado doesn't support my Spartan 6 board.

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00:49пожаловаться #5

2021 November 16

Mahdi Habibi in FPGA technical questions

I see this picture that contains 4 ,6 and g and blue 🔵

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23:31пожаловаться #6

2021 November 19

Onur in FPGA technical questions

Hi guys, is there anyone working with RGB TFT Displays?

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22:50пожаловаться #7

2021 November 21

Foxner in FPGA technical questions

Hi. I'm writing comments for my Verilog code, and I'm wondering:
is there a special term for an enable signal that's produced by a clock divider and that's only ever a single cycle long?

I feel like calling it just an enable signal is a bit vague and doesn't get its purpose and nature across as clearly.
It's really more like a clock signal made of short pulses instead of a square wave.

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00:25пожаловаться #8

Konstantin in FPGA technical questions

Strobe is a common term for single pulse signal

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00:28пожаловаться #9

Foxner in FPGA technical questions

Thanks.

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00:55пожаловаться #10

2021 November 22

Konstantin in FPGA technical questions

Hi folks,

We are looking for an experienced FPGA developer in Alipes, Copenhagen, DK

https://www.alipes.dk/Jobs/Details/10

You are the perfect candidate if you know what is DSP48, XDMA, inference, BRAM, numpy and WNS

Please, apply on the web site on send me a direct message for more information.

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17:30пожаловаться #11