Can anybody suggest a material where I can read about BFM module in high performance bus

Hi. I need to implement a queue. When programming, I'd consider a circular buffer to be the better solution since it doesn't require shifting all the data, unlike with a regular buffer. However I'm wondering if the same is true in HDLs.

In my mind a circular buffer requires comparator logic to determine whether it's full or empty, and it requires both read and write select logic for each byte. A regular buffer on the other hand only needs write select logic for each byte, and it seems that the logic to determine whether the queue is full or empty should be simpler too. As for the shift operation, from my understanding it's a lot cheaper in hardware than in software - just an offset write to the same registers.

Is this correct? Should I use a regular or a circular buffer?

Did you consider regular FIFO buffer? What platform/language do you use?

I'm writing Verilog for Spartan 6.
Is my understanding correct that with a FIFO buffer I'd have to be shifting data all the way through before I could read it out? Meaning there would be latency proportional to the size of the buffer?

nope, not really. The system you are talking about is a Shift Register, with some fixed latency.

But you do not really shift the data in the FPGA FIFO.

FIFO includes BRAM memory for the data and controller, that will handle read and write pointers. So a read latency is constant - 1-2 clock cycles.

I. hope it makes some sense :)

please feel free to ask if smth is not clear

Ah, I see. That's a circular buffer, right?

Precisely :)

Hi. In my Verilog code I have the following parameters:

parameter CLOCK_FREQUENCY=100000000,
parameter BAUD=56000,

and later:

parameter interval = CLOCK_FREQUENCY / BAUD;

The result should be 1786, but the simulation doesn't seem to match that value. I'm generating an enable signal at that frequency (with that interval), and both GTKWave and counter value seem to suggest that the actual value is 2048.

What's could be going on?

Here's the code that's generating the enable signal:

assign uart_enable = !counter;

always @(posedge CLK or posedge RST) begin
    if (RST) counter <= interval;
        else begin
            if (!counter) begin
                counter <= interval;
            end
        counter <= counter - 1;
        end
end

works for me, returns 1785

It did for me too. I had an error in the code that assigned that number.

I should've put that counter decrement inside an else block.

Hi all. We have a problem on installing ise 14.7 on windows 11 . File not installed. This is the error . This software installed up to 85 percent. Can any one find the solution ?

As for as I can remember ise 14.7 is not supported on MS OS since win10 and Xilinx recommend to use VirtualBox VM in this case.

Before we had installed it on win 10 without any problem . But here the installation not complete .