thank you

Hi folks,  I need help with Verilator

Here's my SV mutli-dimensional packed array

logic [8-1:0][16-1:0] mem_a;


After the verilation in the DUT.h it was represented as flatten array

  VL_SIGW(alu__DOT__mem_a,127,0,4);

And in the  VCD dump it's also wide single dimension array

   $var wire 128 ( mem_a [127:0] $end

Is it possible to  preserve multidimensional array representation after the Verilator?

hi guys

do you have tutorial about Vitis and MYIR Zc7020

I find some tutorial but

only tutorial on Xilinx SDK

which is not Vitis

how can FPGA be so energy effient for calculations?

doesnt internal wiring circuitry require energy to keep it on?

In particular: i've checked hash rate per energy for gpu and fpga, and fpga is about 10 times better. But gpu is supposed to be already quite limited hardware

Have anyone implemented UART on fpga?

without any kind of SOCs.

I need some help.

Hi. I have a question regarding designing circuits in Verilog. Is it preferable to write combinational logic as combinational assignments, or should one prefer to write it as sequential logic to utilize high level constructs like branching statements?

For example, I have to describe a fully combinational circuit which includes enable and mode input bits. I figured perhaps using if-else or case statements would make the code more readable, but it would mean that the circuit would have to be put inside an always block, making it less clear that it's entirely combinational and that it shouldn't produce any registers.

Is that a desired practice or should I avoid it? Should I split the design into a combinational and a "sequential" bit, only using the sequential part for branching statements?

you just share your code here

Hi. I have another question. Is there a way to read data from a file at compile time in old (non-system) Verilog? I'd like to create lookup tables for various modules in my design, but I'm wondering whether there's a better solution than hardcoding a bunch of literals into the Verilog file.

Along with that, I'm curious whether there is any way to compute trigonometrical functions at compile time. The whole purpose of the lookup tables in my design is to provide values of sine to the design, and the reason I want to import data from a file is because I haven't found a way to compute the values in Verilog.

generate a define file and it will processed at a compile time

Thanks!

hi guys
i want to compile a matlab codes and simulink by xilinx fpga
plz introduce me a good course about it
tnx

What about google for "xilinx matlab tutorial" ?

Hi everyone

Thanks for giving me a little explanation about subtype