Hi, I have just started learning verilog. I want to get something like this, but my code is not working. Where is the mistake?

module go_fire(input wire clk, output reg [16:0]out, output reg [4:0]clock_divider_out, output reg [16:0]out_out_val);

parameter clock_divider = 2;

reg [16:0] out_val = 0;
reg [3:0] divider_iter = 0;
//integer divider_iter = 0;
//integer out_val = 1;

always @(posedge clk)
begin
if ( divider_iter >= clock_divider)
begin
 out_out_val = out_val;
 clock_divider_out = divider_iter;
 out = out_val;
 out_val = out_val*2;
 divider_iter = 0;
end
divider_iter=+1;
clock_divider_out = divider_iter;

end
endmodule

Hi guys, this group is English only, please respect the rules and other members

First of all, tou must use non blocking
<=
assignment for the registers.
When you use inside always block, then only the last assignment to register will be applied

It's not really clear what functionality you want implement to. Could you please draw the desired waveforms?

something like this

but i got this

we with X find solution. Verilog  use variable=+1 as variable=1. Thanks all

Don't mention wire for input in beginning of code...

Hi, I have just started learning verilog. I want to get something like this, but my code is not working. Where is the mistake?

module go_fire(input wire clk, output reg [16:0]out, output reg [4:0]clock_divider_out, output reg [16:0]out_out_val);

parameter clock_divider = 2;

reg [16:0] out_val = 0;
reg [3:0] divider_iter = 0;
//integer divider_iter = 0;
//integer out_val = 1;

always @(posedge clk)
begin
if ( divider_iter >= clock_divider)
begin
 out_out_val = out_val;
 clock_divider_out = divider_iter;
 out = out_val;
 out_val = out_val*2;
 divider_iter = 0;
end
divider_iter=+1;
clock_divider_out = divider_iter;

end
endmodule

Hello every one , plz suggest me  study material for verilog and system verilog
M a new learner plz suggest which is better for me.

Anyone have system Verilog training videos...

+1

Plz share

hdlbits is a good website to learn verilog

Hi all,
Can somebody help me for frequently asked questions for fpga design engineer position.

Hi everyone, I would like to know the scope of the following job opportunity in future, as I am confused to join the company or not.

Please let me know as I have 2 years experience in FPGA design.

So the job description is follows.




Position: Applications Engineer II.

The Synopsys FPGA Solution incorporates high-quality, high-performance, and easy-to-use FPGA partitioning, implementation, debug, and emulation tools. The Synopsys FPGA Solution allows customers to design low-power, high-performance, and high-capacity FPGA-based production systems and to produce high-reliability designs. Customers also use this solution to prototype ASICs/SoCs with FPGAs, which includes the Synopsys HAPS® FPGA-based prototyping solution.
In this role, you will be part of a team of expert level engineers working with R&D, Field engineers and customers on FPGA products. As a part of the team, you will be involved in Feature Validation, Product Sign-Off, Customer Support and evaluation of FPGA synthesis tools.  
You will also gain expertise in all aspects of FPGA flow including design, testing, synthesis, simulation based verification, functional verification, implementation, P&R and FPGA architecture. You will be involved in defining test strategies and methodologies to continuously improve ease-of use, quality of results and inter-operability with other Synopsys Tools like VCS, DC & Formality and gain expert level knowledge.  By adapting to the recognized best practices and policies in Synopsys, you will also become an expert in various processes involved Product Release Cycle starting from Requirement Specification to Product sign-off.

Responsibilities:
You will be working with product teams in all aspects of the product development cycle including feature validation, bug reporting & validation against releases, analyzing & working on regressions, documentation and providing support to the ACs & customers. You will work closely with Vendors to understand the different requirements for product releases and ensure that the tool meets the different requirements for seamless integration with other Synopsys Tools like Verdi, VCS, Formality etc.

This role is involved in but not limited to the following activities:  

Review of project specifications for new features
Feature Validation against product releases
Development of regression tests
Regular evaluations of product releases
Development and delivery of product documents
Provide post-sale support
Developing training materials and providing trainings for AEs and Customers


Requirements:


B.E./B.Tech/M.Tech/M.E. in Electronics with 2-3 Years of logic and FPGA design experience.
Experience in logic design and implementation using FPGAs.  
Should have very good hands-on experience in Verilog, SystemVerilog and/or VHDL.
Should have good experience in Synthesis, back end flow, FPGA architecture and implementing designs in hardware.  
Exposure to Xilinx/Altera synthesis and Prototyping software is a plus
Excellent communication and inter-personal skills, professional attitude, and strong desire to succeed.
Scripting knowledge is desirable.

Basically the position is validation engineer for FPGA synthesis software

The last lines of job responsibilities shows, it will be like sales and service job. I know synopsys is one of market leaders in providing EDA tools in ASIC synthesis, but for FPGA I don't have any info, how can I see myself if I join there.  This is my concern

/

No, from my experience, this position is not sales and service job, it is more than that. So, go ahead, you will learn a lot and can build your career @ Synopsys