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FPGA technical questions

2021 September 29

H

Hr in FPGA technical questions
Yeah, thank you
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2021 September 30

S1

Sushil Kanike 1DS19E... in FPGA technical questions
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H

Hr in FPGA technical questions
You have 100MHz, 25MHz clocking wizards. You need to generate 50MHz clock, so which clocking wizard you will use ??? And Why?
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p

priyambika in FPGA technical questions
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2021 October 05

MI

Mohammad Ibrahim in FPGA technical questions
Переслано от Mohammad Ibrahim
Can anyone please execute this and check where i am going wrong!?
There are no errors but the output is also not as expected
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MI

Mohammad Ibrahim in FPGA technical questions
Переслано от Mohammad Ibrahim
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MI

Mohammad Ibrahim in FPGA technical questions
Переслано от Mohammad Ibrahim
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MI

Mohammad Ibrahim in FPGA technical questions
Переслано от Mohammad Ibrahim
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MI

Mohammad Ibrahim in FPGA technical questions
Переслано от Mohammad Ibrahim
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MI

Mohammad Ibrahim in FPGA technical questions
Переслано от Mohammad Ibrahim
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MI

Mohammad Ibrahim in FPGA technical questions
Переслано от Mohammad Ibrahim
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AG

Aleksandr Gordeev in FPGA technical questions
HRESETn=1'b0; ?
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MI

Mohammad Ibrahim in FPGA technical questions
It's For negetive reset, right?

N there is no line in FSMcontroller as
HRESETn=1'b0;

Can you please point it out where it is !
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MI

Mohammad Ibrahim in FPGA technical questions
That "H" and "P" suffixes are just for aHb and aPb connection rememberance
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AG

Aleksandr Gordeev in FPGA technical questions
In tb.v you have the "rst" task. HRESETn must be '0' in first time, and HRESETn must be '1' later.

In FSMcontroller.v you have "if(HRESETn)".
Change this as "if(!HRESETn)" at line 21 and line 187.
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MI

Mohammad Ibrahim in FPGA technical questions
Done that 👍
But still i am not getting the expected output 😟
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AG

Aleksandr Gordeev in FPGA technical questions
What is "the expected output"?
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MI

Mohammad Ibrahim in FPGA technical questions
got it , single write in tb was in comment .
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MI

Mohammad Ibrahim in FPGA technical questions
Thanx a lot 🙌
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AG

Aleksandr Gordeev in FPGA technical questions
😂👍
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