1)Yes
2)duly noted.
Will check out your suggestions tomorrow.
Appreciate your help

Hi everyone,
Plz answer following question.

There are 2 serdes parallel data of 66 bits received at 100MHz independent clocks . There is gear box which accepts 67 bits of data, what should be should be output clock, and plz share block diagram.

Thanks.

Appreciate your help.

Tried calibration of the probes but still I am getting a distorted output.
Is there a possibility that my board is faulty?
(Do note on making a GPIO digital high,gave me a straight line with out any noise)
Thank you in advance

It looks like you use trace on pcb with mismatched impedance. But your case is not critical

Any way to verify the possibility?

Check your pcb design in simulation soft at first. Or use expensive special equipment as tektronix DSA8200 for impedance measurement

Try to set matched resistor at far end of your output signal trace

I am trying to bring up Ethernet IP by sending a package from the FPGA to my PC. Vivado version 2019.1, FPGA Zynq-7000 Zedboard I follow the instruction in

1- https://www.youtube.com/watch?v=T8xfkvjbDx8&t=363s

2- https://www.youtube.com/watch?v=C-qEZTk8I94

First, the software stuck at auto-negotiation and I fixed it by setting bit-12 in Register0 (auto negotiation enabled). Once it fixed, the phy works and I can see the package in the WireShark software from PC to the FPGA, but no package from FPGA to PC.
The software stuck at waiting for Rx interrupt, in this line (xemacps_example_intr_dma.c):

\* Wait for Rx indication */

while (!FramesRx);



Does anyone has this issue before? Please help!

does anyone here have experience with these IPs?
- Xilinx Video In to AXI4-Stream
- Xilinx Video Timing Controller
- Xilinx Video Frame Buffer Write

Hi guys,
Does anyone here have experience with Xilinx Video In to AXI-4 Stream ?
I have this design:
Analog camera (PAL) -> ADV7180 (outputs YcbCr 4:2:2 following BT.656 format) -> FPGA
The purspose of my design is just to be able to see the camera streaming on an endpoint like /dev/video*. After that, I will feed the Xilinx DPU with that video streaming.
This is my current design, but I'm not sure how to connect the Xilinx Video In to AXI-4 Stream to the frame buffer ip core.
Can anyone help me to finish this design please ?
Thanks in advance.

It looks like you just simply needed to connect video_out to s_axis_video

Can you expand both of buses?

Hey there
I've used altera before, but I've bought Xilinx spartan-6 and want to use ISE to program it.
The problem is Synthetization takes long time even for 1 line code. about 4-5 minutes.
is it normal?
Thanks

Generally, synthesis is a complex process with several tasks that called in sequence (e.g. compilation, gate placement and connection, timing analysis and optimization, assembling firmware file). I'm not familiar with ISE, but it is not rocket-fast process and on slow machines it can consume time.

On pc with I7-9700 and 16gb ram Vivado could rebuild project such as 10g network adapter with several huge IP's in 15 minutes, afaik.

Yeah, thanks
But altera modelsim with similar code does the job in less than 30 seconds 😅

Would you mind to have a look on spartan7/artix7 xilinx fpga series and switch to vivado instead ?

The thing is that spartan 6 is quite old and is not supported by the vivado toolset. ISE is also deprecated eda for the legacy project. XST, the embedded ise synthesis tool, is dummy and the majority of teams didn't use it for commercial products


Btw, 5 minutes still sounds like too long :)

Thanks👌