S
I hope to keep the block diagram view as my top level. So it's easy to see all the connections between every components.
Size: a a a
2021 January 31
S
I think I finally got to know your proposal after I studied the PG994 and there are two ways to instantiate RTL into a block diagram. One is a simple way called the RTL reference module. The other one is IP Package.
S
It's true that using the RTL reference module way will be much easier if my rtl is simple and may no need to update later.
S
But to think it more. I would prefer to use Processor_reset_module again... Because I think in that module the 2 flipflop should placed more closer which will have less metalstablilty risk. But if I write a 2 ff verilog. I don't know if they may place very far and cause high risk of metalstabiliy. How do you think of it? I just think it in the view of a asic engineer...
I
Stranger
But to think it more. I would prefer to use Processor_reset_module again... Because I think in that module the 2 flipflop should placed more closer which will have less metalstablilty risk. But if I write a 2 ff verilog. I don't know if they may place very far and cause high risk of metalstabiliy. How do you think of it? I just think it in the view of a asic engineer...
You can use "async_reg" attribute to place the ff close. It's a placement constraint
S
Ismael
You can use "async_reg" attribute to place the ff close. It's a placement constraint
Thank you for providing a way of placement constraint. I will Google how to use it👍🏻
S
set_property ASYNC_REG TRUE [get_cells sync_regs*]
It seems that I can add the constraint only in XDC by doing that I could choose not to modify the verilog.
So later I can keep the same verilog used for fPGA and asic.
It seems that I can add the constraint only in XDC by doing that I could choose not to modify the verilog.
So later I can keep the same verilog used for fPGA and asic.
2021 February 01
A
Good day. Sorry for the bad english. Tell me how to make a reversible counter of impulses with a display of the quantity on a two-position 7 indicator? Development environment qwartus 2
2021 February 03
K
Hi guys,
Does anyone have prior experience with Pynq? Here's the question and shared project
https://discuss.pynq.io/t/how-to-access-two-levels-of-hierachy-on-pynq-z1/2297
Does anyone have prior experience with Pynq? Here's the question and shared project
https://discuss.pynq.io/t/how-to-access-two-levels-of-hierachy-on-pynq-z1/2297
DC
which version of pynq are you using with vivado 2020.1 (i.e. 2.6 2.5 or whatever)?
2021 February 04
K
which version of pynq are you using with vivado 2020.1 (i.e. 2.6 2.5 or whatever)?
Hi Davide, 2.5
DC
Hi Konstantin, try to move to pynq 2.6. I found some issues in vivado compatibility versions. Check also the presence of tcl/hwh/xsa, and that all have the same name as the bitstreams file
GJ
What is inference in verilog.
2021 February 05
S
Hi my friends. I am working on a project using xilinx XDMA. But after I modified the example design and then reboot PC, the PC always turn into a blue screen. The blue screen says "Page Fault In Nonpaged Area”. My BAR size is 1M for AxI lite master and my design has axi stream interface. Could somebody has know the familiar issue ⚠️? Any answer is appreciated. Thank you
K
Stranger
Hi my friends. I am working on a project using xilinx XDMA. But after I modified the example design and then reboot PC, the PC always turn into a blue screen. The blue screen says "Page Fault In Nonpaged Area”. My BAR size is 1M for AxI lite master and my design has axi stream interface. Could somebody has know the familiar issue ⚠️? Any answer is appreciated. Thank you
I believe that your question contains a part of the answer :) Roll back the changes your performed and introduce them one by one
S
@vconst89 haha. Yes, you are right. I am on my way to the lab and planning to roll back changes one by one.
2021 February 09
ИЛ
Hello, friends. How can I describe on verilog shift register, realised on block ram? Using megafunctions not situable in my case. Could you recommend manuals with detail describing block ram? I use altera flex 10 ke.
2021 February 10
K
- Mom! Can we buy this quantum computer ?
K
- No! We have a quantum computer at home
Quantum computer at home:
Quantum computer at home: