FS
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2021 March 04
2021 March 08
J
Hi, does anyone know how can I change the DisplayPort interlane alignment order (Xilinx) ?
2021 March 10
H
Thank you
AE
Hi everyone
What is pin Number of Axi_uartlite rx and tx in zedboard. I Read the manual it's mentioned to D11 and c12. However it's didn't detect for this pin.
What is pin Number of Axi_uartlite rx and tx in zedboard. I Read the manual it's mentioned to D11 and c12. However it's didn't detect for this pin.
AE
2021 March 13
YÇ
Hi guys
YÇ
Hi guys, I have a homework with basys3 card in the Vivado design suite ı wonder ıf anyone can help? (He/she can send me a message in my number.)
2021 March 15
N
Hello, where can i find synthesized and packaged example ip-s from the vitis vision library?
2021 March 16
FS
Yusuf Çınarcı
Hi guys, I have a homework with basys3 card in the Vivado design suite ı wonder ıf anyone can help? (He/she can send me a message in my number.)
Hi! what is your request?
YÇ
My application is this
in the Vhdl-Vivado Design suite
When the switch on the Basys-3 development board is switched to 1 position, the led on the development board is required to blink for 1 s (it will turn on continuously for 1 s, turn off for 1 s and continue in the same way
Actually ı did main code but ı didn't find testbench and simulation. If someone know. They can send me a message.
in the Vhdl-Vivado Design suite
When the switch on the Basys-3 development board is switched to 1 position, the led on the development board is required to blink for 1 s (it will turn on continuously for 1 s, turn off for 1 s and continue in the same way
Actually ı did main code but ı didn't find testbench and simulation. If someone know. They can send me a message.
FS
Yusuf Çınarcı
My application is this
in the Vhdl-Vivado Design suite
When the switch on the Basys-3 development board is switched to 1 position, the led on the development board is required to blink for 1 s (it will turn on continuously for 1 s, turn off for 1 s and continue in the same way
Actually ı did main code but ı didn't find testbench and simulation. If someone know. They can send me a message.
in the Vhdl-Vivado Design suite
When the switch on the Basys-3 development board is switched to 1 position, the led on the development board is required to blink for 1 s (it will turn on continuously for 1 s, turn off for 1 s and continue in the same way
Actually ı did main code but ı didn't find testbench and simulation. If someone know. They can send me a message.
oh , im sorry I dont know vhdl yet... im getting more confident with verilog 2005. I wish you luck to find a solution or someone who can help.
YÇ
Okey. Thank you for your answer
2021 March 18
TT
Hi, I’m deploying the physical layer of 4G LTE receiver on FPGA, it has so many processing blocks. Does anyone know is there any open source provides fpga code or HLS code for 4G LTE receiver? Thanks for your help!
2021 March 20
HS
For an integrated circuit PLA having n inputs ,k product terms and m outputs there are?
2021 March 22
K
Hi folks,
A good friends of mine, Russian IT company, is highly interested in the SQL offloading on FPGAs project.
You can easily google a bunch of papers about this topic and a commercial realization, like Swarm64 company.
If you are experienced fpga developer and looking for challenging task to apply your skills, please pm me, we have something to talk about :)
A good friends of mine, Russian IT company, is highly interested in the SQL offloading on FPGAs project.
You can easily google a bunch of papers about this topic and a commercial realization, like Swarm64 company.
If you are experienced fpga developer and looking for challenging task to apply your skills, please pm me, we have something to talk about :)
2021 March 23
SH
Hello everyone,
I am trying to generate square pulses on my FPGA board(xilinx spartan 6).
I have successfully compiled and implmented the system on xilinx system generator,and dumped the code onto my FPGA.
But when I am trying to view the pulses on a DSO,I am getting heavily distorted pulses on the output.
Any help/suggestion about how to go about the problem is very welcome.
Thank you for your time. :)
I am trying to generate square pulses on my FPGA board(xilinx spartan 6).
I have successfully compiled and implmented the system on xilinx system generator,and dumped the code onto my FPGA.
But when I am trying to view the pulses on a DSO,I am getting heavily distorted pulses on the output.
Any help/suggestion about how to go about the problem is very welcome.
Thank you for your time. :)
Х
Sherlock Holmes
Hello everyone,
I am trying to generate square pulses on my FPGA board(xilinx spartan 6).
I have successfully compiled and implmented the system on xilinx system generator,and dumped the code onto my FPGA.
But when I am trying to view the pulses on a DSO,I am getting heavily distorted pulses on the output.
Any help/suggestion about how to go about the problem is very welcome.
Thank you for your time. :)
I am trying to generate square pulses on my FPGA board(xilinx spartan 6).
I have successfully compiled and implmented the system on xilinx system generator,and dumped the code onto my FPGA.
But when I am trying to view the pulses on a DSO,I am getting heavily distorted pulses on the output.
Any help/suggestion about how to go about the problem is very welcome.
Thank you for your time. :)
What period of your signal and bandwidth of your scope?
Distorted mean ringing or smoothing?
Distorted mean ringing or smoothing?
SH
SH
@mgw925
Thank you for your reply.
The 1MHz clock signal.(for the FPGA)
Not sure about the Band width of the scope
I'm attaching the scope output below.
Thank you for your reply.
The 1MHz clock signal.(for the FPGA)
Not sure about the Band width of the scope
I'm attaching the scope output below.
Х
Sherlock Holmes
1) It looks like you use very long wires with a lot of noise added in it. Do you measure directly on the pin of a devboard?
2) Try to calibrate capacitance of your probes with oscilloscope test signal.
2) Try to calibrate capacitance of your probes with oscilloscope test signal.