Телеграмм чат группы proFpga страница 215

2021 January 30

K

This warning says that one of the set_propery constraint is applied to nothing

Try to figure out which constrain is spoiled, ie click on the warning or investigate the constraints you have in xdc

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23:01пожаловаться #1

K

Konstantin in FPGA technical questions

Wizard could leave some constraints which are not valid anymore

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23:02пожаловаться #2

J

Jesus in FPGA technical questions

Konstantin

This warning says that one of the set_propery constraint is applied to nothing

Try to figure out which constrain is spoiled, ie click on the warning or investigate the constraints you have in xdc

that is weird because I have written all the constraints, one by one in the TCL are they are Ok

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23:05пожаловаться #3

K

Konstantin in FPGA technical questions

Jesus

that is weird because I have written all the constraints, one by one in the TCL are they are Ok

Comment out them all :)

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23:06пожаловаться #4

J

Jesus in FPGA technical questions

Konstantin

Comment out them all :)

it happens the same!!! :O

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23:07пожаловаться #5

J

Jesus in FPGA technical questions

but if I remove the ILA, the errors dissapear

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23:08пожаловаться #6

J

Jesus in FPGA technical questions

how that is possible?

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23:08пожаловаться #7

K

Konstantin in FPGA technical questions

Jesus

but if I remove the ILA, the errors dissapear

Try to remove ILA and do not add the core manually, but add through wizard, select lanes - mark as debug

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23:09пожаловаться #8

IS

Ivan Shevchuk in FPGA technical questions

Jesus

but if I remove the ILA, the errors dissapear

problems with constraints, clock/reset description, clock domain crossing or negative slacks...

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23:09пожаловаться #9

J

Jesus in FPGA technical questions

Konstantin

Try to remove ILA and do not add the core manually, but add through wizard, select lanes - mark as debug

yeah, that's what I did. Do you mind if I share with you the project ?

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23:09пожаловаться #10

K

Konstantin in FPGA technical questions

Ivan Shevchuk

problems with constraints, clock/reset description, clock domain crossing or negative slacks...

As author mentioned, it only appears when ILA exists

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23:10пожаловаться #11

K

Konstantin in FPGA technical questions

Jesus

yeah, that's what I did. Do you mind if I share with you the project ?

Yeah, let's try, drop your project here or pm to me

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23:11пожаловаться #12

J

Jesus in FPGA technical questions

Konstantin

Yeah, let's try, drop your project here or pm to me

sent by PM

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23:24пожаловаться #13

J

Jesus in FPGA technical questions

@vconst89 what do you think?

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23:30пожаловаться #14

K

Konstantin in FPGA technical questions

I'll take a look in a following days, probably on monday, sorry man :)

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23:33пожаловаться #15

S

Stranger in FPGA technical questions

Hi. My friend . Just a small question. I want to add a reset synchronizer into the block diagram. I find an IP called processor_reset_module. It seems it has much more ports and functions than my image. Do you agree for timing and resources reason, I should write 2FF synchronizer Verilog and import it as an IP in block diagram instead of using that processer_reset_module?

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23:43пожаловаться #16

2021 January 31

M

Max in FPGA technical questions

Stranger

Hi. My friend . Just a small question. I want to add a reset synchronizer into the block diagram. I find an IP called processor_reset_module. It seems it has much more ports and functions than my image. Do you agree for timing and resources reason, I should write 2FF synchronizer Verilog and import it as an IP in block diagram instead of using that processer_reset_module?

You can add 2ff syncer as simple RTL unit, and write to tcl false path directive. NO reasons for add this simple component as IP core

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00:06пожаловаться #17

M

Max in FPGA technical questions

And no reasons for create ip core for this component. In Vivado you can this as .v/.vhdl source. SystemVerilog isnt supported

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00:07пожаловаться #18

K

Konstantin in FPGA technical questions

Stranger

Hi. My friend . Just a small question. I want to add a reset synchronizer into the block diagram. I find an IP called processor_reset_module. It seems it has much more ports and functions than my image. Do you agree for timing and resources reason, I should write 2FF synchronizer Verilog and import it as an IP in block diagram instead of using that processer_reset_module?

Another option-
Vivado generates top level wrapper verilog file. You may edit and write your FF logic just like in any other verilog file

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00:16пожаловаться #19

S

Stranger in FPGA technical questions

Thank you @vconst89 @masterplayer. To be honest, it's my first time using the Block diagram. So you mean I could generate the HDL wrapper of the 2FF synchronizer and I could add it into the Block diagram view(My top hierarchy is a block diagram project). There is no need to package the 2FF as a new IP. Am my understanding correct?

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02:03пожаловаться #20