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FPGA technical questions

2021 January 30

Hi guys, I have created an AXI4 peripheral using: Tools -> Create and package new IP -> Create AXI4 Peripheral and I would like to put an ILA or something like that to debug, is this possible?

In Vivado? you can add ILA module directly in the RTL or connect probes manually after synthesis

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22:32пожаловаться #1

Jesus in FPGA technical questions

Alex

@Jesus: Do you use Xilinx or Altera/Intel?

I use Vivado

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22:33пожаловаться #2

Jesus in FPGA technical questions

Rob

In Vivado? you can add ILA module directly in the RTL or connect probes manually after synthesis

yes, but I'm using a Zynq with Petalinux

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22:37пожаловаться #3

Alex in FPGA technical questions

Normally I use Altera, but you should be able to connect a chipscope instance

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22:38пожаловаться #4

Konstantin in FPGA technical questions

Jesus

Hi guys, I have created an AXI4 peripheral using: Tools -> Create and package new IP -> Create AXI4 Peripheral and I would like to put an ILA or something like that to debug, is this possible?

If its about IP core interfaces, then open block design with IPcore, select AXI or any other interfaces and mark as debug

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22:42пожаловаться #5

Jesus in FPGA technical questions

Konstantin

If its about IP core interfaces, then open block design with IPcore, select AXI or any other interfaces and mark as debug

I did that, but the tool is not getting the width if the signals, look

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22:44пожаловаться #6

Jesus in FPGA technical questions

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22:44пожаловаться #7

Jesus in FPGA technical questions

@vconst89 you can see at ILA, the width is 1 for all the probes

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22:45пожаловаться #8

Konstantin in FPGA technical questions

If you need to debug internal signal, then consider one of the following steps
- integrate ILA IP core right in your design. Just as usual, in a non-block design mode
- have a look in vivado guide, you can connect ILA after synthesis. It works the same way, you open design, find the desired nets and mark as debug

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22:45пожаловаться #9

Konstantin in FPGA technical questions

Jesus

@vconst89 you can see at ILA, the width is 1 for all the probes

Open ILA configuration and set the desired width of ILA ports

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22:46пожаловаться #10

Konstantin in FPGA technical questions

Jesus