Hello

Hello.  Guys tell me, did anyone buy Cyclone 5 SE / SX chips separately?  Through whom and long delivery times?

Open Source vscode-TerosHDL finally published in the Visual Studio marketplace!

After some beta versions of the IDE and adding some new features like:

- All features extended to VHDL/Verilog/SystemVerilog
- XDC/SDC support
- Improved documentation generation
- Linting (ModelSim, Icarus, Verilator, GHDL, Vivado...)
- Dependencies viewer
- ... and more!

Future work:

- File tree view
- FSM graph
- Simulators backend integration in IDE

https://lnkd.in/eNQzgGb

Hello everyone,
I wanted guidance about using xilinx system generator for electrical drives.

More importantly creating a sine wave in system generator

Could anyone please help me?

Hello friends! How can I make shift register in block memory onto EPF10k130 without megafunctions? Preffered language is verilog.

What does mean azure ?

I want to know how azure connects with teams ?

How does this question relate to FPGA?

Thanks, bot)

Hi, does anyone can help me? I want to add a layer to the Petalinux. The layer's name is: openembedded-core (morty branch)
And I need to add this layer because I want to add python3-pip to my Petalinux: https://layers.openembedded.org/layerindex/recipe/53469/

Hello

a) https://lmgtfy.app/?q=1-bit+basic+full+adder
b) https://lmgtfy.app/?q=full+adder+using+half+adders+scheme
c) https://lmgtfy.app/?q=half+adder+verilog+code
d) https://lmgtfy.app/?q=full+adder+verilog+code

Hi everyone could you please advise me about probe that I can use with zedboard to give clear signals. When I measured the clock of zedboard the signal was like sinusoidal the problem it was with prob. Actually I'm working with F=100mhz which prob is suitable for me. Thank you

The signal
F=100Mhz
V= 1v -100mv
Which kind of prob and feature it will be suitable.