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FPGA technical questions

2020 September 17

Н

Николай in FPGA technical questions
Jesus
any Petalinux expert here?
5) Describe your question well and in detail. Don't make other people guess and ask to clarify the details several times. Respect the time of the people who are ready to help you.

More information on how to ask questions:
    https://www.biostars.org/p/75548/
    http://www.catb.org/~esr/faqs/smart-questions.html
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2020 September 19

J

Jesus in FPGA technical questions
I'm trying to build Petalinux with a opencv 3.3, for doing that, I added this line to petalinuxbsp.conf:
PREFERRED_VERSION_opencv ?= "3.3+%"

then, I copied this file: https://forums.xilinx.com/t5/Embedded-Linux/DPU-Tutorial-2019-1/m-p/1003686/highlight/true#M35583

to [project_folder]/project-spec/meta-user/recipes-support/

but I'm having an error
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J

Jesus in FPGA technical questions
[INFO] building project
[INFO] sourcing bitbake
[INFO] generating user layers
INFO: bitbake petalinux-user-image
Loading cache: 100% |###########################################################################################################################################################################################################################################| Time: 0:00:00
Loaded 3815 entries from dependency cache.
WARNING: /home/jesus/petalinux_2019.1/myd_czu3eg_baidu/project-spec/meta-user/recipes-support/opencv/opencv_3.3.bb: Exception during build_dependencies for cmake_do_configure                                                                                 | ETA:  --:--:--
WARNING: /home/jesus/petalinux_2019.1/myd_czu3eg_baidu/project-spec/meta-user/recipes-support/opencv/opencv_3.3.bb: Error during finalise of /home/jesus/petalinux_2019.1/myd_czu3eg_baidu/project-spec/meta-user/recipes-support/opencv/opencv_3.3.bb
ERROR: ExpansionError during parsing /home/jesus/petalinux_2019.1/myd_czu3eg_baidu/project-spec/meta-user/recipes-support/opencv/opencv_3.3.bb
Traceback (most recent call last):
bb.data_smart.ExpansionError: Failure expanding variable EXTRA_OECMAKE, expression was -DOPENCV_EXTRA_MODULES_PATH=/home/jesus/petalinux_2019.1/myd_czu3eg_baidu/build/tmp/work/aarch64-xilinx-linux/opencv/3.3+gitAUTOINC+87c27a074d_2a9d1b22ed_a62e20676a_34e4206aef_fccf7cd6a4-r0/contrib/modules     -DWITH_1394=OFF     -DCMAKE_SKIP_RPATH=ON     -DOPENCV_ICV_PACKAGE_DOWNLOADED=808b791a6eac9ed78d32a7666804320e     -DOPENCV_ICV_PATH=/home/jesus/petalinux_2019.1/myd_czu3eg_baidu/build/tmp/work/aarch64-xilinx-linux/opencv/3.3+gitAUTOINC+87c27a074d_2a9d1b22ed_a62e20676a_34e4206aef_fccf7cd6a4-r0/ippicv_lnx     ${@bb.utils.contains("TARGET_CC_ARCH", "-msse3", "-DENABLE_SSE=1 -DENABLE_SSE2=1 -DENABLE_SSE3=1 -DENABLE_SSSE3=1", "", d)}     ${@bb.utils.contains("TARGET_CC_ARCH", "-msse4.1", "-DENABLE_SSE=1 -DENABLE_SSE2=1 -DENABLE_SSE3=1 -DENABLE_SSSE3=1 -DENABLE_SSE41=1", "", d)}     ${@bb.utils.contains("TARGET_CC_ARCH", "-msse4.2", "-DENABLE_SSE=1 -DENABLE_SSE2=1 -DENABLE_SSE3=1 -DENABLE_SSSE3=1 -DENABLE_SSE41=1 -DENABLE_SSE42=1", "", d)}     ${@base_conditional("libdir", "/usr/lib64", "-DLIB_SUFFIX=64", "", d)}     ${@base_conditional("libdir", "/usr/lib32", "-DLIB_SUFFIX=32", "", d)}   -DWITH_OPENCLAMDBLAS=OFF -DWITH_OPENCLAMDFFT=OFF -DBUILD_opencv_dnn=OFF -DWITH_EIGEN=ON -DBUILD_opencv_freetype=OFF -DWITH_GPHOTO2=ON -DWITH_GSTREAMER=ON -DWITH_GTK=ON -DWITH_JASPER=OFF -DWITH_JPEG=ON -DWITH_FFMPEG=ON -DWITH_LIBV4L=ON -DWITH_OPENCL=OFF -DWITH_PNG=ON -DPYTHON3_NUMPY_INCLUDE_DIRS:PATH=/home/jesus/petalinux_2019.1/myd_czu3eg_baidu/build/tmp/work/aarch64-xilinx-linux/opencv/3.3+gitAUTOINC+87c27a074d_2a9d1b22ed_a62e20676a_34e4206aef_fccf7cd6a4-r0/recipe-sysroot/usr/lib/python3.5/site-packages/numpy/core/include -DBUILD_EXAMPLES=ON -DINSTALL_PYTHON_EXAMPLES=ON -DWITH_TBB=ON -DBUILD_opencv_text=OFF -DWITH_TIFF=ON -DWITH_V4L=ON which triggered exception NameError: name 'base_conditional' is not defined


Summary: There were 2 WARNING messages shown.
Summary: There was 1 ERROR message shown, returning a non-zero exit code.
ERROR: Failed to build project
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J

Jesus in FPGA technical questions
does anyone can help me ?
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2020 September 20

SH

Sherlock Holmes in FPGA technical questions
Anyone any ideas about how to use simulink with fpga.
It involves using hdl toolbox.
But im unable to figure out the working.
Anyone any tutorial or with experience
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SH

Sherlock Holmes in FPGA technical questions
Or any literature
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Д

Даня in FPGA technical questions
Sherlock Holmes
Anyone any ideas about how to use simulink with fpga.
It involves using hdl toolbox.
But im unable to figure out the working.
Anyone any tutorial or with experience
3) Use respectful communication. Remember that you are among professional engineers.

4) Don't write loads of small messages connected by one thought. Describe your entire question in one big message. This makes it easier to understand information and navigate the discussion.

5) Describe your question well and in detail. Don't make other people guess and ask to clarify the details several times. Respect the time of the people who are ready to help you.
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Д

Даня in FPGA technical questions
Sherlock Holmes
Anyone any ideas about how to use simulink with fpga.
It involves using hdl toolbox.
But im unable to figure out the working.
Anyone any tutorial or with experience
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2020 September 26

K

Kuldeep in FPGA technical questions
Hi all,

I am looking for suggestions or tutorial on " use of MMCM with GTH" in ZCU MOSOC Xilinx

Please suggest
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2020 September 27

A

Andrew in FPGA technical questions
Hi, what info are you expecting to get?
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K

Kuldeep in FPGA technical questions
How to connect mmcm to GT?
I mean where to use MMCM primitive or should I go for clocking wizard with GT wizard IP
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K

Kuldeep in FPGA technical questions
Andrew
Hi, what info are you expecting to get?
I am looking to supply 72MHz clock using external Oscillator to GT Quad in xilinx
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A

Andrew in FPGA technical questions
Kuldeep
How to connect mmcm to GT?
I mean where to use MMCM primitive or should I go for clocking wizard with GT wizard IP
Did you try to instantiate GT IP into Vivado and then open Example design to see how it’s done by Xilinx ?
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K

Kuldeep in FPGA technical questions
Yes
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K

Kuldeep in FPGA technical questions
Andrew
Did you try to instantiate GT IP into Vivado and then open Example design to see how it’s done by Xilinx ?
Yes
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2020 September 28

MK

Murali Kumar in FPGA technical questions
All about FPGA - session 2
---------------
Click and know how familiar you are with FPGA basics
Submit your valuable response

https://docs.google.com/forms/d/e/1FAIpQLScRkN-r9F32oJZuvclbuXsTstA79FBLb_f98F9prwxGpoPgiQ/viewform
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K

Konstantin in FPGA technical questions
Murali Kumar
All about FPGA - session 2
---------------
Click and know how familiar you are with FPGA basics
Submit your valuable response

https://docs.google.com/forms/d/e/1FAIpQLScRkN-r9F32oJZuvclbuXsTstA79FBLb_f98F9prwxGpoPgiQ/viewform
Is it an interview quiz you were offered to pass?
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MK

Murali Kumar in FPGA technical questions
Not like that

I have created a practice test

From this one can collect different answer and share some answers to the group
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MK

Murali Kumar in FPGA technical questions
All about FPGA - session 1
Basics in digital
Evaluate yourself and Submit your valuable response

https://docs.google.com/forms/d/e/1FAIpQLSdzC3TII4yMlz0wj1zF_Y_Xj7r_TLhs07pMiA_bhlnLju1DCw/viewform
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K

Konstantin in FPGA technical questions
Murali Kumar
Not like that

I have created a practice test

From this one can collect different answer and share some answers to the group
Why should I be interested in answering your quiz? :)
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