It depends on what you want to do. If you're developing a simple application, then create a Petalinux image that boots on your platform, and package that to use in Vitis. If you need drivers and all that stuff, because you're doing multimedia apps and/or you don't know much about embeded Linux to customise your kernel builds, then downgrade the entire project version so it matches your BSP version.

The BSP is supposed to give you a bootable and working software OS for specific board. All the Xilinx drivers (XRT, etc) are supposed to be working out of the box. AFAIK, is not suggested to use old BSP scripts in a new Petainux release. What I'll do if I want to focus on developing the application and not in solving end-to-end issues with my software components, is to work with elements that are fully compatible (in this case, downgrade everything to 2019.1).

Good evening. Anybody has experience with USB 3.0 on FPGA (5Gb/sec, super speed mode). For my home project I want to use USB 3.0 to data exchange with PC.
1) How realistic is it to fit a USB stack into an FPGA and how many LUTs will it take?
2) What can you advise as a PHY? Searching by component is pretty depressing.

As far as I know Xilinx does not officially support USB.  You will have to setup transceivers by yourself, which might be challenging. You didn't mentioned what FPGA you're planning to use but generally speaking it's quite realistic to fit USB into FPGA.

What about FT602Q? That realize USB 3.0 <-> 32-bit FIFO to FPGA.

You have 3 options here:
1) Using USB stack IP core (bought or self-written) with some external transceiver
2) Cypress FX3
3) FTDI FT601 or FT602 for UVC applications

For option 1  I recommend TUSB1310 from Texas Instruments

FT602 can be used in UVC applications only, for regular bulk transfers you should use FT601

does anyone know why the Memory interface device frequency is fixed? I want to modify it

I was expecting this:

Hello everyone
I wrote a simple code for xc95144xl xilinx cpld but in impact after initial chain and detecting the cpld there are not any available choices in Impact Processes panel and so I can not program and erase and .... . what is the problem? does that mean that my programmer does not support this cpld? My programmer is xilinx DLCV10 Jtag programmer.

If I go to output menu and create svf file then the choices are available and I can program but it does not really program the cpld/

Hi all! Do you know how to format a systemverilog code in visual studio code, with a formatter similar to the SystemVerilog’s Sublime package? Thanks!!

You can add a request feature:
https://github.com/TerosTechnology/vscode-terosHDL/issues

any Petalinux expert here?

A little