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FPGA technical questions

2020 August 18

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Andrey S in FPGA technical questions
Abdalwahab Essa
What is the bandwidth of your oscilloscope?
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Abdalwahab Essa in FPGA technical questions
1 ghz
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Abdalwahab Essa in FPGA technical questions
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Andrew Kushchenko in FPGA technical questions
Abdalwahab Essa
The clk in zedboard is it pulse or sinusoidal ?
Its a pulse. But your oscilloscope broke the signal edges
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Abdalwahab Essa in FPGA technical questions
Why that happens Actually I'm using 100mhz frequency from the clk
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Abdalwahab Essa in FPGA technical questions
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Abdalwahab Essa in FPGA technical questions
By using this cable
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Andrei Kondratev in FPGA technical questions
Abdalwahab Essa
Why that happens Actually I'm using 100mhz frequency from the clk
Because you are using long ground wire?
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Dmitry Kovalenko in FPGA technical questions
There are the test square wave source and the ground output on the oscilloscope, check them with the same probe. If the square wave looks fine, your issue is not about oscilloscope.
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Х in FPGA technical questions
Abdalwahab Essa
The clk in zedboard is it pulse or sinusoidal ?
May be some digital filter in oscilloscope enabled?
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Murali Kumar in FPGA technical questions
Abdalwahab Essa
This is crct only ...


Whatever clk generated from oscillator or any source it will be look like sine wave.

If you are taking a clock from FPGA after FF's then it will be look like a square
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Murali Kumar in FPGA technical questions
Dmitry Kovalenko
There are the test square wave source and the ground output on the oscilloscope, check them with the same probe. If the square wave looks fine, your issue is not about oscilloscope.
This will helps to check the scope
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2020 August 19

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Jesus in FPGA technical questions
Hi guys, what's the difference between the DSA and the XSA?
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India in FPGA technical questions
Hi can anyone share me info how to convert c or c++ code into vhdl code in vivado
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Konstantin in FPGA technical questions
India
Hi can anyone share me info how to convert c or c++ code into vhdl code in vivado
Have a look on Vivado HLS demos , it produces verilog from specifically written C/CPP code.
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Konstantin in FPGA technical questions
Hi, am I right that Xilinx Vitis and Intel OneApi shares the same idea - to give an FPGA as a backend for software developers?
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Konstantin in FPGA technical questions
And what is the conceptual difference between SDK for OpenCL and Open API tools? It seems that they have the same behind them https://www.intel.com/content/www/us/en/software/programmable/sdk-for-opencl/overview.html
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2020 August 22

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Carlos in FPGA technical questions
We have released a new beta version of TerosHDL VSCode, an open source HDL IDE. It includes Wavedrom support in the Documentation Generator

https://github.com/TerosTechnology/vscode-terosHDL/releases/tag/v0.0.3
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Carlos in FPGA technical questions
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Konstantin in FPGA technical questions
Awesome! Thanks for sharing
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