V
Hi everyone! Could somebody tell me, is it possible to get ports list (black_box) from Quartus .qxp file?
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2020 July 29
2020 July 31
J
Does anyone here own a Ultra96 board?
2020 August 05
J
Hi. Can you recommend me any alternative board to the Ultra96v2?
2020 August 09
ИЛ
I using Z-turn board.
ИЛ
AX7350 may be interesting for you too.
ИЛ
DE0-NANO may be situable too. But it made on CycloneV.
M
Hi. Can you recommend me any alternative board to the Ultra96v2?
J
I have already bought that board. I think it is much better than Ultra96v2.
Do you have it?
Do you have it?
M
I have already bought that board. I think it is much better than Ultra96v2.
Do you have it?
Do you have it?
No, i don't have it. But it looks nicer in theory, PCI-E, more I/O and RAM.
2020 August 14
J
Hi, does anyone know why the *Presets button* does not appear to me ?
J
I was expecting this:
P
Are you using a Xilinx official board? Maybe the board files for that specific one has no presets
J
Pablo
Are you using a Xilinx official board? Maybe the board files for that specific one has no presets
The part I'ved used to create this project is: xczu3eg-sfvc784-1-e
P
If you created a design from scratch (just selecting the FPGA and not a board) there are no presets for the board as Vivado doesn't know what is connected.
If you start the design using the template of one of Xilinx's boards (ZCU102/ZCU04/etc...) you will probably see the preset option as Xilinx's already knows the speed and size of the DDR RAM as well as the available peripherals mounted on the board
If you start the design using the template of one of Xilinx's boards (ZCU102/ZCU04/etc...) you will probably see the preset option as Xilinx's already knows the speed and size of the DDR RAM as well as the available peripherals mounted on the board
J
Pablo
If you created a design from scratch (just selecting the FPGA and not a board) there are no presets for the board as Vivado doesn't know what is connected.
If you start the design using the template of one of Xilinx's boards (ZCU102/ZCU04/etc...) you will probably see the preset option as Xilinx's already knows the speed and size of the DDR RAM as well as the available peripherals mounted on the board
If you start the design using the template of one of Xilinx's boards (ZCU102/ZCU04/etc...) you will probably see the preset option as Xilinx's already knows the speed and size of the DDR RAM as well as the available peripherals mounted on the board
No. You are wrong
J
Pablo
If you created a design from scratch (just selecting the FPGA and not a board) there are no presets for the board as Vivado doesn't know what is connected.
If you start the design using the template of one of Xilinx's boards (ZCU102/ZCU04/etc...) you will probably see the preset option as Xilinx's already knows the speed and size of the DDR RAM as well as the available peripherals mounted on the board
If you start the design using the template of one of Xilinx's boards (ZCU102/ZCU04/etc...) you will probably see the preset option as Xilinx's already knows the speed and size of the DDR RAM as well as the available peripherals mounted on the board
The presets (as you can see in the pics) are for the Zynq IP core, not for the board itself. For the board itself, what you usually get from the vendor, are the "board definition files". Don't get confused about both concepts.
The problem I'm experiencing appears only in Vivado 2020.1, and not in the previous versions.
The problem I'm experiencing appears only in Vivado 2020.1, and not in the previous versions.
2020 August 18
AE
The clk in zedboard is it pulse or sinusoidal ?
AE
