Size: a a a

FPGA technical questions

2020 June 19

Д

Даня in FPGA technical questions
Amjed
Hi my friends
I want to learn design communication systems by FPGA, such as OFDM, wavelet, ....
Are there examples about this projects??
I need that...
I will be thankfull.
источник
2020 June 21

S

SMSJ in FPGA technical questions
Hello every one
I want to implement a vhdl code on a cpld of max 9000 series of Altera and I found that I should use max plus 2 software for these series.But there is an error about numeric_std package and I understood that this software does not support numeric_std package.So how can I implement add operation or any other arithmetic operation on this cpld?Does any other software like Quartus 9 support these series? Or have you any other idea for that?
источник

AK

Andrew Kushchenko in FPGA technical questions
SMSJ
Hello every one
I want to implement a vhdl code on a cpld of max 9000 series of Altera and I found that I should use max plus 2 software for these series.But there is an error about numeric_std package and I understood that this software does not support numeric_std package.So how can I implement add operation or any other arithmetic operation on this cpld?Does any other software like Quartus 9 support these series? Or have you any other idea for that?
I think you can use std_logic_unsigned library for implement the add operation between two std_logic_vector signals. Also you can use std_logic_signed for signed arithmetic
источник

K

Konstantin in FPGA technical questions
SMSJ
Hello every one
I want to implement a vhdl code on a cpld of max 9000 series of Altera and I found that I should use max plus 2 software for these series.But there is an error about numeric_std package and I understood that this software does not support numeric_std package.So how can I implement add operation or any other arithmetic operation on this cpld?Does any other software like Quartus 9 support these series? Or have you any other idea for that?
источник

S

SMSJ in FPGA technical questions
Andrew Kushchenko
I think you can use std_logic_unsigned library for implement the add operation between two std_logic_vector signals. Also you can use std_logic_signed for signed arithmetic
Thanks
источник

S

SMSJ in FPGA technical questions
🙏🏻
источник

S

SMSJ in FPGA technical questions
Thanks for your answering.I would try both of these ways and inform you about the result.
But can you check if quartus 9 support max 9000? I searched for that but I couldnt find a list of cplds supported by that.I wanted to ask you check it if you have quartus 9 installed on your windows
источник
2020 June 22

RB

Roman Belenkov in FPGA technical questions
Good day! Is it possible to see the timings (slack, hold, etc.) of a particular module from a project using timequest?
источник
2020 June 24

F

Foxner in FPGA technical questions
Hi. Can I ask a telecommunications related question here?
источник

EB

Evgeniy Bolnov in FPGA technical questions
Foxner
Hi. Can I ask a telecommunications related question here?
just ask a question
источник
2020 June 26

F

Foxner in FPGA technical questions
I'm trying to implement unipolar symmetric single-channel communication, and I am unable to listen and transmit at the same time (I can only listen to the medium when I'm transmitting a logical 0). I wonder, are there any protocols out there that already implement something of this sort, or does anyone know how I could go about coming up with one? The thing that baffles me is how to initiate a connection. Both devices need to detect each other, and get their clocks in sync, but they cannot detect a collision when both are transmitting a logical 1.
источник
2020 June 29

K

Konstantin in FPGA technical questions
The fantastic  book is finally generally available now!

Efficient Processing of Deep Neural Networks
This tutorial covers all aspects of model software and hardware design related to the this topic. Explain very key concepts of weight/output/input/row stationarities and dataflow, power budget tradeoffs and hardware-software co-design aspects.
источник
2020 July 07

AE

Abdalwahab Essa in FPGA technical questions
Hi everyone, could you advice me PLZZ. I want to receive signal from the application by zedboard. The signal in khz and mv. Could I find conector using SMA to PMOD the sma is input because I want to receive by pmod. Thank you
источник

Х

Х in FPGA technical questions
Abdalwahab Essa
Hi everyone, could you advice me PLZZ. I want to receive signal from the application by zedboard. The signal in khz and mv. Could I find conector using SMA to PMOD the sma is input because I want to receive by pmod. Thank you
adc module?
источник

AE

Abdalwahab Essa in FPGA technical questions
Yes
источник

AE

Abdalwahab Essa in FPGA technical questions
Thank you sir
источник

Х

Х in FPGA technical questions
What frequency and voltage ranges you need to measure?
источник

AE

Abdalwahab Essa in FPGA technical questions
Frequency Mhz and Khz the.
Voltage mV  and maximum around 1 v
источник

Х

Х in FPGA technical questions
Abdalwahab Essa
Frequency Mhz and Khz the.
Voltage mV  and maximum around 1 v
#Aliexpress US $18.58  10%OFF | High-Speed AD Module AD9226 MSPS ADC 12bit FPGA Development Board Expansion 65MSPS data Acquisition
https://a.aliexpress.ru/_BUF8Rx
источник

Х

Х in FPGA technical questions
I think this will be suitable for you
источник