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FPGA technical questions

2020 February 01

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SR in FPGA technical questions
Please share,  Anybody have DDR4 Verification interview questions
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2020 February 02

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SR in FPGA technical questions
How memory chip controller interact with Dram(DDR) controller in ASIC??
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2020 February 03

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Dmitry Smekhov in FPGA technical questions
Abdalwahab Essa
Hi hello, I want to write code can generate sequences of pulse by using text file by vhdl code. I want to play by time duration and pulse width. Im using zedboard with vivado software. Could I get your help. Thank you.
What is the problems?
Do you want to get a plan of this development?
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2020 February 04

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Abdalwahab Essa in FPGA technical questions
Yes sir I want advice how can created if there is any example that will allow Good.
Thank you sir, 🙏
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adha Adha in FPGA technical questions
Sir,which FPGA is suitable for basic image processing
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Leonid Ivanov in FPGA technical questions
adha Adha
Sir,which FPGA is suitable for basic image processing
I've succeded with the lowest Cyclone V chip. I think Cyclone III/IV also will be suitable. It depends on your image source.
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Kostya Goodsoul in FPGA technical questions
adha Adha
Sir,which FPGA is suitable for basic image processing
you need to understand at least three basic things:
1) video interfaces and i/o you might need: camera links, display port, sdi or whatever
2) what type of processing you want to perform? Go and check logic utilization/requirements for video processing IPs from Intel or Xilinx
3) What's the data stream to process? HD and 8K video will require different FPGAs
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Michael Korobkov in FPGA technical questions
Kostya Goodsoul
you need to understand at least three basic things:
1) video interfaces and i/o you might need: camera links, display port, sdi or whatever
2) what type of processing you want to perform? Go and check logic utilization/requirements for video processing IPs from Intel or Xilinx
3) What's the data stream to process? HD and 8K video will require different FPGAs
Just 5 characters...intel
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adha Adha in FPGA technical questions
My project is just implementation of median filter technique on any image
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adha Adha in FPGA technical questions
Impulses noise image
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Х in FPGA technical questions
adha Adha
My project is just implementation of median filter technique on any image
Try to find chip with enough block memory for one frame))
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adha Adha in FPGA technical questions
Is Spartan 3 is ok
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Sherlock Holmes in FPGA technical questions
Any one know how to do a pwm in verilog in Spartan 6?
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Х in FPGA technical questions
Sherlock Holmes
Any one know how to do a pwm in verilog in Spartan 6?
Using counters? Which frequency and quantization you need?
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Konstantin in FPGA technical questions
Sherlock Holmes
Any one know how to do a pwm in verilog in Spartan 6?
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Konstantin in FPGA technical questions
Welcome to the Internet, let me be your guide here
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Dmitry Smekhov in FPGA technical questions
Abdalwahab Essa
Yes sir I want advice how can created if there is any example that will allow Good.
Thank you sir, 🙏
Ок.
1. Create small testbench with name stand. It must  generate clock, such on ZedBoard, parameters for impuls and receive impuls.
2. Create component, with name for example: impulse_gen.
It must have several ports:
- clk — clock
- reset
- imp_period - bus for setting period
- imp_width - bus fir setting impulse width
- impuls_o - it is your impulse
3. Insert impulse_gen into stend.
You must run the simulation session and you must view no impulses.
Which simulator do you prefer ?

I notice - simulation is very important. You must start development with create design for simulation.

4. Create a counter for period into impulse_gen
5. Create another counter for width

By this step you will create simple component for generating the impulse.
On the next step - setting parameter from zynq.
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Sherlock Holmes in FPGA technical questions
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Using counters? Which frequency and quantization you need?
By comparing a triangular wave with a square wave.
So.that the duty cycle can be variable
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Х in FPGA technical questions
Sherlock Holmes
By comparing a triangular wave with a square wave.
So.that the duty cycle can be variable
Is it pwm or audio dac?
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Sherlock Holmes in FPGA technical questions
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Is it pwm or audio dac?
Pwm
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