Abdalwahab Essa
Yes sir I want advice how can created if there is any example that will allow Good.
Thank you sir, 🙏
Ок.
1. Create small testbench with name stand. It must generate clock, such on ZedBoard, parameters for impuls and receive impuls.
2. Create component, with name for example: impulse_gen.
It must have several ports:
- clk — clock
- reset
- imp_period - bus for setting period
- imp_width - bus fir setting impulse width
- impuls_o - it is your impulse
3. Insert impulse_gen into stend.
You must run the simulation session and you must view no impulses.
Which simulator do you prefer ?
I notice - simulation is very important. You must start development with create design for simulation.
4. Create a counter for period into impulse_gen
5. Create another counter for width
By this step you will create simple component for generating the impulse.
On the next step - setting parameter from zynq.