The latest ISE is 14.7

Hello!  What is the maximum transmit / receive bandwidth on pcie avmm Cyclone V core without DMA?  4 lines, Gen 2. Avmm bus 128 bit, 125 MHz

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Package UtilsPkg;
//something
Endpacage

Q: when I 'import UtilsPkg::*' in several modules all testbenchers say 'conflict with previous package declaration of UtilsPkg'

Do I must include the package or import it?

UtilsPkg:
function int GetBitNun(input int sz);
int nBits=1;
while(sz > 2**nBits)
nBits+=1;
return nBits;
end function //GetBitNum

4ex:
FILE_SIZE 32
ADDR_WIDTH GetBitNum('FILE_SIZE)

Include is a pre-processor directive "copy paste this file here". So when you make include, you literally define the same package in different places. That's the reason of your conflict

I tried include and import and I take the same result. The true message I'll send later.
I use AldecHdl

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Could someone help me with this?

I'm porting VUnit to XSim

Has anyone here worked on the wireless open access research platform before?

I'm not familiar enough with xsim, but maybe your cmdline for launching simulation lacks some dumping option? And therefore database is empty

Please tell me:
How to know testcases are passed at last phase in uvm

I want to see log messages only reached to last phase