There should be dedicated message, like "TESTCASE PASSED"

Here Verbosity not helpfull?

If you not confident that test get into the report phase, you could use some uvm_debug feature of simulation tool in gui mode. It will show in what phase your test is running

No, I think not

Thank you @Ruslan_Dalidovich

How to know verification code is correct or wrong, if wrong how to debug(sb and uvm)

Hmm, basically you should run your testcase in debug mode with gui enabled, add signals of interest to the waveform and look through simulation - stimulus that applied should match the expected stimulus; analyze log messages - there could be testbench related errors or fatal errors; You can put breakpoints in your code and debug step by step and use uvm_debug tool in simulator to look through the phases, objections etc

Thank you👍

How to know reading data is correct or wrong from DDR4 and usb 3.0

And writing too

You can know about correct or wrong read from DDR if you use ECC mode.

👍

How to override in sv like override(create() ) in uvm.

For writing also same??  how I can confirm the transferred data to memory and wrote data into memory is same or not

There are two situations:
1. You have some design and you want to create a test infrastructure.  You send special test data, receive the data back and compare with the expect data.

2. You want send ant receive real data (no test) and you want to confirm no errors in the data.
 
What do you want?

1 point only. While testing Manually need to receive data after wrote data or automatic receive data??

Why I am asking means I read some where. after wrote the data into memory,The PHY layer receive data what wrote into memory and compared with transferred data to memory are same or not??

Please clarify me

On my boards I use the path:
1. There is a test generator in the fpga. It generates a random sequence.
2. Memory controller write and read data in the memory. My memory controller works as big FIFO.
3. Data from memory is translated to host computer. Program checks the data with  the estimated data.

@dsmv2011 Thank you👍

Hi hello, I want to write code can generate sequences of pulse by using text file by vhdl code. I want to play by time duration and pulse width. Im using zedboard with vivado software. Could I get your help. Thank you.