A
Parameter value =7
Reg [value -1: 0] xo
Wire y0
y0=|xo
What hardware will it gen erate for value =1 ?
Reg [value -1: 0] xo
Wire y0
y0=|xo
What hardware will it gen erate for value =1 ?
Size: a a a
2019 December 16
A
Interview question👆
K
X0- Array of range [0:0], single wire. Reduce or function from x should be X so you will have direct connection from x0 to y0
2019 December 17
A
Thanks.
PI
Hi all,
Please share docs of SoC verification platforms using HW emulation and co-modeling Testbench technologies
Please share docs of SoC verification platforms using HW emulation and co-modeling Testbench technologies
2019 December 19
JR
Does anyone have any codes or good articles on image watermarking?
2019 December 22
H
• The Overall architecture of the Audio processing System
• Prepare the differential equation and a block diagram for each Audio
effect.
• Explain in detail the function of each system.
• Prepare the differential equation and a block diagram for each Audio
effect.
• Explain in detail the function of each system.
2019 December 24
A
Cool
2019 December 29
H
Can anyone give me the code for delay audio effect?? Please
K
Can anyone give me the code for delay audio effect?? Please
Could you please give a bit more technical information?
Х
Can anyone give me the code for delay audio effect?? Please
2 port memory enough
K
Simple FIFO with read starting from certain threshold ( delay value) should work fine for this task
H
Could you please give a bit more technical information?
So I’m designing an audio system that takes an audio system and adds one of the 5 audio effects . And one of the effects is delay, i need help on the vhdl code
2019 December 30
AN
So I’m designing an audio system that takes an audio system and adds one of the 5 audio effects . And one of the effects is delay, i need help on the vhdl code
You can try use - two independent clock fifo (xilinx fifo ip core for example)
PB
Can anyone help me about how display an image on vga in vhdl?
AN
So I’m designing an audio system that takes an audio system and adds one of the 5 audio effects . And one of the effects is delay, i need help on the vhdl code
Or make create self delay module based on shift registers as this https://surf-vhdl.com/how-to-implement-a-shift-register-in-vhdl/
2020 January 01
MK
Моё почтение господа
H
How do i write port maps for components of vhdl codes??
PB
Name : component_name port map (comp_in => entity_in , comp_in2=> entity_in2, comp_out => entity_out) ;