Х
Sherlock Holmes
Pwm
Which frequency and bit-size of signals?
Size: a a a
2020 February 04
2020 February 05
SH
Which frequency and bit-size of signals?
Of the order 5-10khz no idea of the bit size
Х
Sherlock Holmes
Of the order 5-10khz no idea of the bit size
pwm <= w_triag > w_sqr;
or what do you need?
or what do you need?
2020 February 07
I
Can any one give me the code of a qpsk transmitter and receiver
I
In vhdl
2020 February 10
PB
Can anyone have a simple Quad SPI code in VHDL?
PB
I have artix7 board
K
Try to start with Xilinx QSPI core https://www.xilinx.com/products/intellectual-property/axi_quadspi.html Generate design in Vivado Block Designer and ILA and VIO block to control it and observe the results
PB
I want to access SCK with STARTUPE2
K
You can manually add STARTUPE2 into BD wrapped
R
Does anyone have a full user manual for the Bittware XUS-P3S board? Or any other additional information (xdc pinout, control utilite, etc)?
I
How much of you use vhdl in the casual job, friends?
K
How much of you use vhdl in the casual job, friends?
Better run a poll :) btw, I do
2020 February 13
J
The benefits of removing reset from your design are: fewer timing paths, performance and the ability to infer more dedicated hardware.*TRUEFALSE
The CLB flip-flop supports active low CE, active low SR and asynchronous/synchronous set/reset port.*TRUEFALSE
The CLB flip-flop supports active low CE, active low SR and asynchronous/synchronous set/reset port.*TRUEFALSE
J
What do you think about the answers?
J
I think both are false
K
I think both are false
1. True, you really should use less reset in fpga design as possible
2. True, read a ug474
2. True, read a ug474
K
