A
2. Somewhat, first step - make IP core for PCM2DSD, and several experiments with upsampling
Size: a a a
2019 November 25
A
perhaps it will be a more accurate analogue
2019 November 26
PI
Is there any other ways to write last line of the code please suggest
2019 November 28
Н
Hi! Has anyone worked with the ice40up Lattice family?what library should be connected to active-hdl, for simulation of ip hardware
[
[
HSOSC, for example]
2019 November 30
7S
Hi....system generator token - how to delete a Hardware Co-Simulation from the list
2019 December 03
D
#VitisAI has been released today at the #xdf2019 and is available for download now.
In a nutshell: it is the tool that takes your trained #tensorflow or #caffe model and optimises it for your #Xilinx hardware.
Or very simply spoken: the turbocharge for #versal-devices and their AI engines.
In a nutshell: it is the tool that takes your trained #tensorflow or #caffe model and optimises it for your #Xilinx hardware.
Or very simply spoken: the turbocharge for #versal-devices and their AI engines.
Д
#VitisAI has been released today at the #xdf2019 and is available for download now.
In a nutshell: it is the tool that takes your trained #tensorflow or #caffe model and optimises it for your #Xilinx hardware.
Or very simply spoken: the turbocharge for #versal-devices and their AI engines.
In a nutshell: it is the tool that takes your trained #tensorflow or #caffe model and optimises it for your #Xilinx hardware.
Or very simply spoken: the turbocharge for #versal-devices and their AI engines.
I tried to installed but it’s size is like my ex gf (>100GB)
D
I tried to installed but it’s size is like my ex gf (>100GB)
vitis-ai-tools-1.0.0-cpu.tar.gz 3,3G
vitis-ai-tools-1.0.0-gpu.tar.gz 5,3G
vitis-ai-runtime-1.0.1.tar.gz 4,6G
2019 December 04
DG
There was a question about tetris on FPGA.
Unfortunately it was in Russian.
Therefore question and following humor and flood were deleted.
Unfortunately it was in Russian.
Therefore question and following humor and flood were deleted.
DA
Why you kik Alex??
ΔΒ
the comments there are also in russian, therefore the link should be banned 😃
// ÐÏÌÅ Ó ÔÅËÕÝÉÍ ÂÌÏËÏÍ
logic [`FIELD_EXT_ROW_CNT-1:0][`FIELD_EXT_COL_CNT-1:0][`TETRIS_COLORS_WIDTH-1:0] field_with_cur_block;
D
the comments there are also in russian, therefore the link should be banned 😃
// ÐÏÌÅ Ó ÔÅËÕÝÉÍ ÂÌÏËÏÍ
logic [`FIELD_EXT_ROW_CNT-1:0][`FIELD_EXT_COL_CNT-1:0][`TETRIS_COLORS_WIDTH-1:0] field_with_cur_block;
upvote
DG
2019 December 05
DS
Can anyone have suggestions, Which FPGA development board will be good enough to have with three USB 3.0 IP, where two of them wil be use a device and another will be use as host.
2019 December 09
AE
Hi everyone
I want to generate PWM signals the make output. However I want to received this signal do Date logging in soc Zedboard board I'm still beginner. Actually I have do pwm signals but I want to learn the second part to do all in one program. I have using vivado with soc zedboard. I want your advice and help.
Thank you,
I want to generate PWM signals the make output. However I want to received this signal do Date logging in soc Zedboard board I'm still beginner. Actually I have do pwm signals but I want to learn the second part to do all in one program. I have using vivado with soc zedboard. I want your advice and help.
Thank you,
AE
I want to do signal processing after I do Date logging. Thank you
2019 December 10
K
Abdalwahab Essa
Hi everyone
I want to generate PWM signals the make output. However I want to received this signal do Date logging in soc Zedboard board I'm still beginner. Actually I have do pwm signals but I want to learn the second part to do all in one program. I have using vivado with soc zedboard. I want your advice and help.
Thank you,
I want to generate PWM signals the make output. However I want to received this signal do Date logging in soc Zedboard board I'm still beginner. Actually I have do pwm signals but I want to learn the second part to do all in one program. I have using vivado with soc zedboard. I want your advice and help.
Thank you,
If you are doing an educational project, try to connect target signals to ILA (https://www.youtube.com/watch?v=_ljXMoGJ5iM ). ILA core is a kind of logic analyzer inside FPGA. See Ch.10 here https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_3/ug908-vivado-programming-debugging.pdf
AE
Many thanks sir