A
Are cs and wr driven with the same clock domain (clk)?
Reg process and signal tap instance are driven with the same clock.
Double checked timing violations: nothing for mentioned signals.
What about clock domains, cs and wr are originated from different domains. Cs belongs to slow clock domain, and wr belongs to faster domain (the same as clk signal). Wr is triggered for one clk period in order to allow writing data while cs, regaddr and data are stable.
