For Altera?

What exactly do you want to build?

I would like to build I2C converter for USB

Maybe I should choose Stm32 for my task?

I assume that would be easier to implement :)

How it can be easy, if it is very sophisticated MC?

AVR is much simple

Normally the chip/boards manufactors provide a library (c/c++ funitions) for you

Shouldn't be that hard, you could also use a raspberry pi

I am interested in USB interface, hardware implementation of it

In this case: a fpga might be the right choice

Does someone know library for USB for Altera

I'm not an expert in this case, but if you wanna use USB in FPGA you need an external PHY with ULPI interface. For ULPI interface a lot of companies, such as Altera have an IP. But it has some payment if you need more than just experiment. The second way is using one of SoC's, which have hardware implementation of USB, but it was an MCU/CPU realization anyway. Take STM32 with USB and I2S. It will be faster, simpler and cheaper for you. Also, you can read this article for USB 3.0 realization: https://numato.com/kb/usb-3-0-a-cost-effective-high-bandwidth-solution-for-fpga-host-interface/

Maybe it help

Verilog Audio Controller  is a basic audio controller providing I2S, SPDIF, and DAC outputs.
Simple to drive AXI4-L register interface, with built in 2048 entry buffer and interrupt on programmable threshold.

Features
   ▫️SPDIF tx supporting 16-bit data @ 44.1KHz or 48KHz
   ▫️I2S master (SCK, SDATA, WS)
   ▫️2 channel sigma-delta DAC outputs
   ▫️AXI4-L register interface
   ▫️8KB RAM buffer inferred (maps to BRAM)
   ▫️Programmable interrupt threshold
   ▫️Single interrupt output

https://github.com/ultraembedded/core_audio

#I2S #SPDIF #DAC #audio #verilog
@ipcores

Lightweigth USB Core -  core that would be similar to the SIE you find in classic microcontrollers that support USBs. That means it requires a soft core to implement the actual USB stack, the hardware itself only handle up to the transaction layer of USB.

It's designed to be small but still allow full flexibility of what kind of device it implements, supports all types of transfers, all packet sizes and any combination of end points without having to change the hardware configuration at all.

Features:
  ◦ 10 BRAM, 390 FF and 530 LUT4
  ◦ Clocked at 48 MHz
  ◦ Wishbone interface for the CSRs and Buffer Descriptors

Links:
  ◦ Doc
  ◦ Src

#USB #iCE40 #FPGA #verilog #PHY

Hi, one question, does anyone know how (in a Vivado "block design"), I can connect a pin to VCC (that is, set it to logic 1)?

Choose constant block from the ip catalogue

Thanks

Hi Pal. Have anyone tried xilinx pcie IP called XDMA? I am new to it and failed to install it driver on window 10 PC.  .. Could someone share experience on using it?