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FPGA technical questions

2021 January 05

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S@M in FPGA technical questions
I mean no need for real fpga to implement it in real time
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2021 January 06

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Fabiano Silos in FPGA technical questions
What type of problems you guys think I can face that can be fixed inside a netlist file ? Am I supposed to be worried about this file or you guys think I dont need to worry about this file once it is automatically generated? Im asking this because I want to know If there are cases when I need to manually change what is inside this file. Thank you!
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Andrew in FPGA technical questions
Fabiano Silos
What type of problems you guys think I can face that can be fixed inside a netlist file ? Am I supposed to be worried about this file or you guys think I dont need to worry about this file once it is automatically generated? Im asking this because I want to know If there are cases when I need to manually change what is inside this file. Thank you!
Why would you change anything in a netlist file?
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Fabiano Silos in FPGA technical questions
Andrew
Why would you change anything in a netlist file?
That was my original question :)
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Fabiano Silos in FPGA technical questions
You need to read the whole thread where me and Engineer talk about it.
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Fabiano Silos in FPGA technical questions
to understand why we were talking about that.
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Andrew in FPGA technical questions
Where is this thread?
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Konstantin in FPGA technical questions
I'm pretty sure that you can perform any change in the netlist with proper RTL code, synthesis attributes, constraints and synthesis settings
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Fabiano Silos in FPGA technical questions
Andrew
Where is this thread?
omg, im so sorry for that.
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Fabiano Silos in FPGA technical questions
I wrote for you as If I were in the channel where this thread happened.
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Fabiano Silos in FPGA technical questions
let met take the link.
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Fabiano Silos in FPGA technical questions
Переслано от Engineer
There is a step known as Engineering Change Order, ECO. This is when there is a requirement to change or fix the functionality of the netlist. Doing it by hand is very painful depending on the size of the patch that needs to be applied. You need to do Logical Equivalence Checking, LEC which is faster than doing a netlist simulation, to make sure the generated netlist is functionally equivalent to the RTL HDL code. But you still do need to do gate level simulations which can take a long time as LEC cannot catch everything. However, your question does not seem to understand, the vast costs involved in having a dead design back from the fab.
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Fabiano Silos in FPGA technical questions
this is the start of the thread. since I cannot send a link directly to the thread it is in this channel:
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Fabiano Silos in FPGA technical questions
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Konstantin in FPGA technical questions
Fabiano Silos
this is the start of the thread. since I cannot send a link directly to the thread it is in this channel:
Could you please formulate your questions, what sort of changes do you need to perform in the netlist ?
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Konstantin in FPGA technical questions
It doesn't make a lot of fun to jump over inconsistent threads
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Fabiano Silos in FPGA technical questions
Konstantin
Could you please formulate your questions, what sort of changes do you need to perform in the netlist ?
Im sorry Konstantin, since the previous thread I mention already triggered on me a lot of things... I cannot continue in this for now. Anyways I appreciate your help. thank you!
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Konstantin in FPGA technical questions
Yw
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Fabiano Silos in FPGA technical questions
Guys Im new to this world. My head is blowing right now.
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Fabiano Silos in FPGA technical questions
doing my homework here. I will come back for sure :)
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