There is a step known as Engineering Change Order, ECO. This is when there is a requirement to change or fix the functionality of the netlist. Doing it by hand is very painful depending on the size of the patch that needs to be applied. You need to do Logical Equivalence Checking, LEC which is faster than doing a netlist simulation, to make sure the generated netlist is functionally equivalent to the RTL HDL code. But you still do need to do gate level simulations which can take a long time as LEC cannot catch everything. However, your question does not seem to understand, the vast costs involved in having a dead design back from the fab.