It's impossible to predict. The compilation time depends on the structure and density of the design, the values of operating frequencies, the timing constraints requirements, and of course, on the location of the stars in the sky. 😄

There has to be a certain way

Only the experience of compiling a similar designs.  😭

Start compile you design with no time constraints at all or with very low frequencies for preliminary timing estimate.

All i know is only max. frequency

Which os are you using?

I'm linux you can run

# time vivado file.v

It will demand relatively the same time for similar projects if you let it alone while compiling

I guess you can find similar methods in other kind of OS

I am using xilinx ise suite

What is your target FPGA? ISE is not supported by Xilinx for years and it doesn't make any sense to use it today except for an old legacy projects

I guess you are talking about not the synthesis time, but algorithm execution time?

No just simulation

Yes

Well, there are several things you should keep in mind
- frequency of your pipeline, or one clock period. For 200MHz you its 5ns
- latency of your pipeline. How long does it take for your sample to travel through your pipeline. For example, for 15taps FIR fulter latency will be = 7
- space between samples, or sample rate. In case of FIR filter you can latch  new input on every clock. But let's say you implemented your 15taps FIR filter with only 1 DSP unit, i.e. its fully sequential. In this case it will take 15 clock periods before you will be able to latch a new input

FPGA design is about continuous tradeoffs of these parameters, different algorithms call for different solutions. It will be easier to help you  if you share your code

Then through away ISE and switch to vivado :) or try some open source tools, like ghdl/verilator/gtkview

Thank you

Yes  vivado is better
But they ask me to do it in ise

Thanks

So is it your digital circuit design course project?

Yes