K
najmi na knopku i polu4i6 rezultat
i tvoja me4ta osu6e6tviiiiiiiiiiiiza
Size: a a a
2020 March 24
K
najmi na knopku i polu4i6 rezultat
i tvoja me4ta osu6e6tviiiiiiiiiiiiza
i tvoja me4ta osu6e6tviiiiiiiiiiiiza
Are speaking perl ?
D
Are speaking perl ?
fluently
K
Abdalwahab Essa
The connection correct everything correct but can't read the hardware
Did it help you?
AE
yes i have press on open target
AE
AE
Same problem no hardware
I
Abdalwahab Essa
Hi everyone I have install vivado I have connect with my hardware but didn't read the hardware
Have you installed the cable drivers?
AE
i didnt do that befor just install vivado only
I
If you are on Linux the drivers are not installed automatically. Yo have to install them after vivado. I don't know in Windows, but it seems to be something related to the cable drivers
AE
thank you sir i will search on this proble maybe it will be because that.
2020 March 26
RB
Good afternoon! How to recalibrate the EMIF core on Stratix 10?
K
Good afternoon! How to recalibrate the EMIF core on Stratix 10?
You can use External Memory Interface Debug Toolkit during debug session to request recalibration of the interface. Another option is to use Local_reset_req signal.
For more details pls check External Memory Interface IP user guide for Stratix 10
For more details pls check External Memory Interface IP user guide for Stratix 10
RB
Local_reset_req did not give a result. After the start of the system, the configuration of the Si5340 clock generator begins. After the configuration is complete, the success and fail signals of the emif kernel are zero. local_reset_done is also null. I tried to export the Quartus Prime EMIF debug toolkit interface, but could not find the register map anywhere
2020 March 27
SR
How to increase simulation window in xilinx ise from 1000ns to 3000 ns
Д
Ctrl + mouse scroll
SR
Thank you
2020 March 28
A
Ok hi there this is ankit
A
Ok thanks