Sensibility list is nothing about synthesis - well, in intelfpga and Xilinx synthesis doesn’t watch on it during synthesis. So, it only has meaning in modeling. Since you want to improve your modeling part, keep in sensitivity list only signals which are in if/case condition

So, by “keep scheme works” do you mean it’s implementation in fpga, or you are talking about results of your modeling?

Yeah, thanks. You've explained my thought better than me

I just need to model my behavior part in active-hdl, using only one signal.

Testbench, of course.

Technically sensitivity list is kind of unfair logic - from one point of view your design wouldn’t be synthesized due to an errors
From another point of view - it doesn’t matter in synthesis
It is a hollywar theme I guess

If you are talking about this code - you use latches, that’s not pretty good)

Not sure about this cause it is my question to laboratory task.

You create simple multiplexers, you can do them without process

Ok, thanks, Try to correct my mistakes.

This code will be latch only in case of incomplete sensitivity list. But it looks complete , so I believe it will be nice combinatorial mux

Do you need to have it as a sequential logic with clock?

Then instead of
Process ( list)

Write
Process(clk) begin
If rising_edge(clk) then

((Switching logic)))

End if;
End process;

Not sure about incomplete sensitivity list. On model it can behave like a latch but would not be a latch but wouldn't be synthesized as a latch
latch is:

process(all)
begin
if (en = 1) then
d_out <= d_in;
end if 
end process

mux:

process(all)
begin
if (en == 1) then
d_out <= d_in;
else:
d_out <= d_in2;
end if
end process

process(all)
begin
if (en = 1) then
d_out <= d_in;
end if 
end process

Yes, you are right

I am a Computer Science student, and am relatively new to VDHL. I am trying to make a Serdes. I am having some problems.
1. The code in Github contains 4 files—
           Serdes_Top.vhd
           Serdes_Top_tb.vhd
           Serializer.vhd
           Deserializer.vhd
   So how do I open the project in my Xilinx ISE Design together
2. How do I make a multi file serdes project and how do I connect           serializer to deserializer.
3. And why is there training the data
Thank You

0. Xilinx ISE is not supported anymore, if you don't need it for some good reason, switch to Vivado
1. Go to Vivado, create new project. Add your files into sources. _tb.vhd will be "simulation" file and rest of other "synthesis"
2. Now you can start synthesis with serdes_top as a top-level and simulation with serdes_top_tb as top
3. Have a look on TB file, it should contain ser-deser connected one to another

Hi everyone I have install vivado  I have connect with my hardware but didn't read the hardware

The connection correct everything correct but can't read the hardware