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FPGA technical questions

2020 March 02

K

Konstantin in FPGA technical questions
So warning should not stop your simulation. at least if you didn't change this option manually
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A in FPGA technical questions
Konstantin
Here's from GHDL manual :

http://ghdl.free.fr/ghdl/Simulation-options.html
--assert-level=LEVEL
Select the assertion level at which an assertion violation stops the simulation. LEVEL is the name from the severity_level enumerated type defined in the standard package or the ‘none’ name.
By default, only assertion violation of severity level ‘failure’ stops the simulation.
No I'm not changing it
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A in FPGA technical questions
I don't understand why it remains to 0ms
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Konstantin in FPGA technical questions
And what is your simulation resolution?

Try to remove your CPU instantiation, to exclude all possible problems inside it.

Also - since 1993 you don't have to declare component before entity instantiation :)
https://insights.sigasi.com/tech/four-and-half-ways-write-vhdl-instantiations/
labelname: entity work.entityName(architectureName)
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A in FPGA technical questions
Konstantin
And what is your simulation resolution?

Try to remove your CPU instantiation, to exclude all possible problems inside it.

Also - since 1993 you don't have to declare component before entity instantiation :)
https://insights.sigasi.com/tech/four-and-half-ways-write-vhdl-instantiations/
labelname: entity work.entityName(architectureName)
Can you make me an example with my MIPSCPU component, please
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A in FPGA technical questions
It's interesting
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Konstantin in FPGA technical questions
For those who are interested


The real error was in

C:\Program Files (x86)\Ghdl\bin\ghdl.exe:info: simulation stopped @0ms by --stop-delta=5000

It means that signal didn't achieve stable state after 5000 delta cycles.
The reason was combinatorial loop. See here for more information
https://lauri.xn--vsandi-pxa.com/hdl/primitives/sr-latch.html

It happened because the same signal was used both as input and output of the combinatorial chain.
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Konstantin in FPGA technical questions
 alu_execute    :  entity work.ALU
   port map (
     OP_idx      =>  aluOp_in,
     In1        => readData1_in,
     In2        => sAluData,
     OutZ        => sZero,
     OutRes      => sAluData
   );

Instead of

 alu_execute    :  entity work.ALU
   port map (
     OP_idx      =>  aluOp_in,
     In1        => readData1_in,
     In2        => sAluData,
     OutZ        => sZero,
     OutRes      => sAluRes
   );
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India in FPGA technical questions
Any one have drone based radar target simulator ppt Or document for reference
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2020 March 07

AE

Abdalwahab Essa in FPGA technical questions
HI Could you PLZ help me to got this Books
1- The Zynq Book: Embedded Processing with the Arm Cortex-A9 on the Xilinx Zynq-7000 All Programmable Soc
2-The Zynq book tutorials : for Zybo and ZedBoard
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Aleksandr Gordeev in FPGA technical questions
Abdalwahab Essa
HI Could you PLZ help me to got this Books
1- The Zynq Book: Embedded Processing with the Arm Cortex-A9 on the Xilinx Zynq-7000 All Programmable Soc
2-The Zynq book tutorials : for Zybo and ZedBoard
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AG

Aleksandr Gordeev in FPGA technical questions
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AG

Aleksandr Gordeev in FPGA technical questions
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AE

Abdalwahab Essa in FPGA technical questions
Thank you so much sir 😊 👍
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2020 March 08

TG

Tarbă George in FPGA technical questions
Hello guys i neted some help to program a board fpga for mining
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AN

Alexander Nepryaev in FPGA technical questions
Tarbă George
Hello guys i neted some help to program a board fpga for mining
Which problem do you have?
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Doka in FPGA technical questions
Tarbă George
Hello guys i neted some help to program a board fpga for mining
What kind of HW do you have?
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2020 March 09

I

Ivan in FPGA technical questions
always_ff @ (posedge clk)
ff <= ~ff;
global global(ff, halfclk);

What is a VHDL analog of 'global'?
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Konstantin in FPGA technical questions
Ivan
always_ff @ (posedge clk)
ff <= ~ff;
global global(ff, halfclk);

What is a VHDL analog of 'global'?
Declare signal inside package and it will be available for assign and reading in any entity,  where this package was imported

But it's for sure for tb only
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Ivan in FPGA technical questions
create_generated_clock -name {halfclk} -divide_by 2...
The global construction connect generated clock to the clock pin of the handler clb:
always_ff @ (posedge halfclk)
dothejob();
Pardon for calambure
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