AE
HI everybody .... when i launch to SDK i got this problem
Size: a a a
2020 March 16
K
Abdalwahab Essa
HI everybody .... when i launch to SDK i got this problem
K
downgrade OS version?
Microsoft cancelled support of Win7 a month ago :(
K
Does anybody know, what kind of waveform viewer is used here? https://www.systemverilog.io/generate#conditional-generate
K
Is it GTKWave?
A
A
Avnet Minized board with small OLED display..
A
Started exploring
2020 March 17
R
Does anybody know, what kind of waveform viewer is used here? https://www.systemverilog.io/generate#conditional-generate
its Synopsys DVE
J
its Synopsys DVE
Yes
DF
Hi all! I hope everything is going well!! I am implementing a design with Aurora 64b66b on a vup. I am using 1 lane of a gty transceiver. I also implement an ibert design to play with the gty parameters and find the parameters that better “open the eye” :) Do you know how can I apply such parameters on the Aurora-based design? Thanks!!
2020 March 23
NB
Hi, guys. I've recently got a question like that: what is list of sensibility in vhdl and what singular signal should i remain to keep my scheme works? https://pastebin.com/yktEywQP
Д
Hi, guys. I've recently got a question like that: what is list of sensibility in vhdl and what singular signal should i remain to keep my scheme works? https://pastebin.com/yktEywQP
Sensibility list is about modeling - just to keep modeling task easy for modelsim
So use vhdl-2008 and write process(all)
So use vhdl-2008 and write process(all)
NB
all is not an answer.
K
all is not an answer.
Hi Nick, we respect each other here and we expect the same from you. Please, be polite, if you wish to receive help here. What you are trying to describe in your VHDL code looks like combinatorial logic and
all is definitely an answer for you. If you need something differ, please provide more explanationsNB
I'm sorry for my unpleasant answer. I don't wanna be rude.
NB
Explanation: i need to remain only one signal in my list of sensibility to keep scheme works. Answer is clock-signal, but i can't explain why it is so.
K
I believe you should provide the full text of your task
NB
So, there is full text.
K
One signal is expected to be clock if this case, but your current process describes combinatoral logic, not the sequential one