DG
SR
No, I am expecting realtime(who are worked) answer for this
Ban
Size: a a a
2020 February 23
2020 February 28
S
How can I implement kalman filter in an FPGA board using veriloghdl code?
NH
Matrix + Floating point
aA
And where the mistake happened
aA
Any body how to debug it
K
adha Adha
Any body how to debug it
Don't post vertical shots, respect other people
Add ILA (chipscope, debug monitor) on your microblaze input reset, make sure that you connected clock and reset signals properly
Add ILA (chipscope, debug monitor) on your microblaze input reset, make sure that you connected clock and reset signals properly
2020 February 29
AS
Hey any one working on 5G user equipment development?
2020 March 02
A
Hi all, I have a problem in a ghdl simulation, it doesn't start and I get a very long list of this warning:
../../src/synopsys/std_logic_arith.vhdl:255:20:@0ms:(assertion warning): There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).It reamins to 0ms. The problem is that I don't know how to understand which is the operand that make this warning, first of all
K
Hi all, I have a problem in a ghdl simulation, it doesn't start and I get a very long list of this warning:
../../src/synopsys/std_logic_arith.vhdl:255:20:@0ms:(assertion warning): There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).It reamins to 0ms. The problem is that I don't know how to understand which is the operand that make this warning, first of all
No worries about it. https://www.csee.umbc.edu/portal/help/VHDL/packages/std_logic_arith_syn.vhd It happens when you put signal with X (undefined) bits into arithmetic function. At the very beginning of your simulation, all your signals (except explicitly initialized) are XXXX, so you have this warning. It's not critical, no worries about it. Some simulators have option to disable it
K
Hi all, I have a problem in a ghdl simulation, it doesn't start and I get a very long list of this warning:
../../src/synopsys/std_logic_arith.vhdl:255:20:@0ms:(assertion warning): There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).It reamins to 0ms. The problem is that I don't know how to understand which is the operand that make this warning, first of all
A
No worries about it. https://www.csee.umbc.edu/portal/help/VHDL/packages/std_logic_arith_syn.vhd It happens when you put signal with X (undefined) bits into arithmetic function. At the very beginning of your simulation, all your signals (except explicitly initialized) are XXXX, so you have this warning. It's not critical, no worries about it. Some simulators have option to disable it
Ok but the simulation doesn't proceed
K
Ok but the simulation doesn't proceed
Could you please send you simulation and compile log files? I don't think this warning should stop your simulation. Probably you have another ERROR or FATAL assertions
A
Could you please send you simulation and compile log files? I don't think this warning should stop your simulation. Probably you have another ERROR or FATAL assertions
A
this is compile log and simulation
K
Well, that's true :) No more warnings. And what about your top level testbench? Do you use
std.stop somewehre? https://www.doulos.com/knowhow/vhdl_designers_guide/vhdl_2008/vhdl_200x_small/ ?A
Well, that's true :) No more warnings. And what about your top level testbench? Do you use
std.stop somewehre? https://www.doulos.com/knowhow/vhdl_designers_guide/vhdl_2008/vhdl_200x_small/ ?Uhm nope, I can send the file
K
Here's from GHDL manual :
http://ghdl.free.fr/ghdl/Simulation-options.html
http://ghdl.free.fr/ghdl/Simulation-options.html
--assert-level=LEVEL
Select the assertion level at which an assertion violation stops the simulation. LEVEL is the name from the severity_level enumerated type defined in the standard package or the ‘none’ name.
By default, only assertion violation of severity level ‘failure’ stops the simulation.