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FPGA technical questions

2019 September 02

OL

Oleksandr Ladyzhenskyi in FPGA technical questions
Hello! I working with DAC1401D125 in interleaved mode. For this i use this IP https://github.com/pavel-demin/red-pitaya-notes/blob/master/cores/axis_red_pitaya_dac_v1_0/axis_red_pitaya_dac.v All working correct. On first output generating sinus, on second cosinus.
I want to generate on second output constant voltage. For this i modified 36 row - assign to int_dat_b_wire constant value. But it does not work.
Can you advice something or help with this?
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2019 September 05

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Jesus in FPGA technical questions
do you know why we always have less coverage in Transition Delay Fault than in stuck-at fault ?
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Jesus in FPGA technical questions
Another question. If you have a system with jitter and you are sampling using a CDR, when will your system fail?
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2019 September 11

J

Jesus in FPGA technical questions
Which techniques do you use to reach a high coverage % when testing fault modes?
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EU

Egor Uttsov in FPGA technical questions
Hi all. Does anybody faced with problems to boot HPS (Cyclone V) from flash s25fl512s (Cypress)?
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NITHESH in FPGA technical questions
Anyone has 4b/5b encoding Verilog code
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NITHESH in FPGA technical questions
Pls send
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NITHESH in FPGA technical questions
Anyone knows 4b/5b encoding logic
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Doka in FPGA technical questions
NITHESH
Anyone has 4b/5b encoding Verilog code
try to use case to implement this table
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NITHESH in FPGA technical questions
Ur telling case(data sequence)
4'do<=5'd29 like this
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NITHESH in FPGA technical questions
My question is how 4bit is mapped to 5bit code
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NITHESH in FPGA technical questions
Any one know BMC encoder
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NITHESH in FPGA technical questions
Logi
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NITHESH in FPGA technical questions
NITHESH
Any one know BMC encoder
Anyone pls tell
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Д

Даня in FPGA technical questions
NITHESH
Ur telling case(data sequence)
4'do<=5'd29 like this
Yes
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2019 September 12

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NITHESH in FPGA technical questions
NITHESH
My question is how 4bit is mapped to 5bit code
How this is done ?
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NITHESH in FPGA technical questions
Can you please explain
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DG

Denis Gabidullin in FPGA technical questions
NITHESH
How this is done ?
Stop asking the same question again.
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NITHESH in FPGA technical questions
Okay
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Jesus in FPGA technical questions
Does anyone here has experience with scan interface?
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