u a welcome

Colleagues, I have a question about the synthesis of RAMB36E1 xilinx primitive.

working with the family of Artix 7. Model: xc7a35ticsg324-1L

If I work in Vivado under Linux, my code

 reg [31: 0] mem [0: 16383];

is synthesized successfully, but when I change the width from 16383 [2 ^ 14] to 32767 [2 ^ 16], then an error occurs (see screenshot). Primitive RAMB36E1 supports address widths up to 16 (32767, see screenshot 2)

If I run this hdl code in Vivado on Windows, then there is no such error.

Vivado for Linux and Windows version 2016.4
what could be the problem?

https://www.xilinx.com/support/documentation/user_guides/ug473_7Series_Memory_Resources.pdf

 reg [31: 0] mem [0: 16383];

First FAE answer: try another (fresh) EDA version.
2016.4 is outdated

I try 2018.1 this not help

quick and dirty workaround:
you might to make necessary netlist (RAM) in vivado win and then use it on your target host system

maybe RAM with 16bit addr bus doesnt function properly even in vivado win.
who know?

Hi doka

 reg [31: 0] mem [0: 16383];

Hi Nikolay. I don't know the answer, but if I were you I would check type overflow. I.e. Vivado in windows and Linux may use different parser of the source code and when you set bitwidth equal to 32768 it exceeds int16 datatype. Try ti replace literal value with

localparam RAM_LEN = 32767

and check if it works with 17000 and 32766 values

localparam RAM_LEN = 32767

Thanks, i will try it

U there

Data is coming serially.
If data - >1 then my output should be
1-0-1 this toggling should happen in half the period.
If total time period of clock is 10ns
Toggling should happen within 5ns

How to implement this logic

localparam RAM_LEN = 32767

it didn't help, but it was an interesting idea. I'll look for materials on this topic, the results will be reported, I think someone it will be useful
Thanks for your help

I'm wondering what could be the reason for your case because I  googled no similar case. If it was a common problem, I expect many people should have encountered it. Let us know if you find the solution :)

Hello! Selling boards Xilinx zynq - 7000.
Almaty city, price 200$

Hello! has anyone worked with soft-processor microaptiv up  from MIPS ? What development tools did you use for soft developing? (I don't like the MIPS open IDE option very much and am looking for an alternative)

None of the fuckers dono

Your question sounds like a student task, so if you need a help, you have to provide a more detailed description. What language are you going to use, what does "->" operator mean. Also, it makes sense to provide the desired waveform drawing. And if you don't stop swearing and insulting other people, you will be kicked off from this group.