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FPGA technical questions

2019 August 12

MdcEn_n is not mentioned anywhere else in the file. How can this piece of code be valid, if MdcEn_n is not defined in the module?

this signal generated in eth_clockgen.v
https://github.com/xfguo/ethernet_tri_mode/blob/master/rtl/verilog/miim/eth_clockgen.v

and MdcEn_n input for eth_outputcontrol and eth_shiftreg

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20:03пожаловаться #1

Foxner in FPGA technical questions

Roman Yanalov

This is a strange verilog feature. It is possible to use 1bit wire without its definition

Ah, that must be it then, thanks!

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21:19пожаловаться #2

2019 August 13

Andrey S in FPGA technical questions

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16:08пожаловаться #3

Andrey S in FPGA technical questions

Lattice programmer, made with FTDI (FT2232H) board.
ADBUS0 -> TCK
ADBUS1 -> TDI
ADBUS2 -> TDO
ADBUS3 -> TMS

Working with Lattice Programmer without additional software/programming. Just connected wires :)

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16:08пожаловаться #4

Andrey S in FPGA technical questions

Board is about $10 at aliexpress

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16:13пожаловаться #5

2019 August 17

Arun Malik in FPGA technical questions

hello everyone, i have artix 7 speed grade -2, and hdmi ip core of xilinx PG235 says artix 7 devices are capable of all hdmi 1.4 resolutions

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10:54пожаловаться #6

Arun Malik in FPGA technical questions

and hdmi 1.4 supports 4k 30 fps, but the gt transrecievers of artix 7 are capable of 5.6 Gbps while 4k 30fps is certainly more than that

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10:55пожаловаться #7

Andrew Kushchenko in FPGA technical questions

Arun Malik

and hdmi 1.4 supports 4k 30 fps, but the gt transrecievers of artix 7 are capable of 5.6 Gbps while 4k 30fps is certainly more than that

Did you read timing specification for 4k 30fps for the hdmi? Which pixel clock this required?

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16:08пожаловаться #8

Arun Malik in FPGA technical questions

297 mhz

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16:30пожаловаться #9

Andrew Kushchenko in FPGA technical questions

In this case you will have 2970 Mbit/s data rate at each line with single channel transfer

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17:25пожаловаться #10

Arun Malik in FPGA technical questions

oh okay, I was comparing with the total throughput

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17:44пожаловаться #11

Arun Malik in FPGA technical questions

Arun Malik

oh okay, I was comparing with the total throughput

rookie 😅

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17:44пожаловаться #12

Arun Malik in FPGA technical questions

anyway thanks for helping

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17:45пожаловаться #13

Andrew Kushchenko in FPGA technical questions

Arun Malik

oh okay, I was comparing with the total throughput

Hdmi use 3 data lane each for read, green and blue color components respectively. At one moment it send all color components from one pixel

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17:58пожаловаться #14

2019 August 18

Arun Malik in FPGA technical questions

👍

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10:04пожаловаться #15

Ask Q in FPGA technical questions

Does anybody have a pcie g1 soft core? or maybe found it.

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17:02пожаловаться #16

2019 August 19

Aleksandr Kriukov in FPGA technical questions

I have a task to develop PCI 2.1 device. Please tell me how to implement the clocking scheme. What to use as a clock for the PCI controller? Is it necessary in the case of using 33 MHz to set the triggers to avoid metastability at the input pins PCI? And what to read to understand this (metastability, what and when is necessary and how will be better)?

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14:47пожаловаться #17

Ivan in FPGA technical questions

Take your pencil and write it out. Great hand made😁

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17:17пожаловаться #18

2019 August 23

Jesus in FPGA technical questions

I want to make a check in a testbench:

if (TB_serializer_top.data_input_memory [(count_words_sent * 10) -1: (count_words_sent-1) * 10] == txdp_ShiftReg)

as you see, I check if a piece of array is equal to another
but the piece of the first array is defined by an integer that I have called count_words_sent
that count_words_sent int is defined at runtime, so VCS is giving me an error
Do you know any way to do this?
That is the error that VCS gives me

The range of the part select is illegal:
   Unknown range in part select.data_input_memory [((count_words_sent * 10) -
   1): ((count_words_sent - 1) * 10)]

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01:20пожаловаться #19

Ruslan in FPGA technical questions

Jesus

I want to make a check in a testbench:

if (TB_serializer_top.data_input_memory [(count_words_sent * 10) -1: (count_words_sent-1) * 10] == txdp_ShiftReg)

The range of the part select is illegal:
   Unknown range in part select.data_input_memory [((count_words_sent * 10) -
   1): ((count_words_sent - 1) * 10)]

Try vector bit select, setting the range with +: operator like vect[msb_base_expr +: width_expr], first part msb_base_expr could be changed during runtime:
[(count_words_sent * 10) +: 10] IEEE Std 1800-2012 § 11.5.1

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11:44пожаловаться #20