T
Synchronous clock domains are phase locked, asynchronous clock domains aren't.
Size: a a a
2019 June 24
T
You can provide an external 100MHz clock, and an external 50MHz clock, and tell the tools either that clock A and B are totally separate (no guarantees about their relationship) or that they are locked to some phase offset.
2019 June 25
J
Travis
Synchronous clock domains are phase locked, asynchronous clock domains aren't.
You're right
A
Please tell me what i need to read as introduction for understanding how to solve problem of clock domain crossing.
A
If possible can you send links.
AB
Please tell me what i need to read as introduction for understanding how to solve problem of clock domain crossing.
Google -> Cummings metastability/asynchronous fifos etc
A
There are a lot of no concrete links. And if somebody will send recommendations like this please it is better to keep question unanswered.
A
Sorry that i am so blunt.
AG
There are a lot of no concrete links. And if somebody will send recommendations like this please it is better to keep question unanswered.
AG
there are several articles about CDC and async fifo
AG
and a lot of other excelent papers. Strongly recomend)
A
So good, thanks)
DM
Anyone here worked with python camera module
DM
With Zynq board
DM
I have some doubts regarding this
2019 June 26
J
There are a lot of no concrete links. And if somebody will send recommendations like this please it is better to keep question unanswered.
Cummings paper for CDC is like the Bible of CDC
J
One question. How would you generate clock jitter in a testbebch?
J
I have seen these two ways, but I am not sure if they are the best ways:
J
always
#(period/2+$random(-jitter/2,jitter/2) ) clk = ~clk;
#(period/2+$random(-jitter/2,jitter/2) ) clk = ~clk;
J
always #(period/2+$dist_uniform(seed,-jitter,jitter)) clk0=~clk0;