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Are you trying to create physical layer of lte?
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2019 June 05
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Physical layer of LTE can be implemented with special hardware like USRP, LimeSDR with PC software. And they don't use 1GHz clock.
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USRP is with Xilinx Spartan, LimeSDR - Altera Cyclone IV
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NITHESH
I'm not using PLL by using MMCM u can't do
But you can generate 1 GHz clk for CLKOUTPHY
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Physical layer of LTE can be implemented with special hardware like USRP, LimeSDR with PC software. And they don't use 1GHz clock.
... only for Gigabit Ethernet or USB3.0
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And, ofc, carrier frequency.
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But it is generated not in FPGA.
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NITHESH
Virtex xc7z045
but it is Zynq, not Virtex, or not?
KA
NITHESH
Virtex xc7z045
XC7Z045 is just a SoC with Kintex-7 FPGA
ZH
Is ir possible to copy the generated vhdl code from vivado hls and paste it into quartus to run it over cyclone 4 for example?
M
Is ir possible to copy the generated vhdl code from vivado hls and paste it into quartus to run it over cyclone 4 for example?
if it generates architecture-agnostic vhdl code (i.e. no Xilinx primitive instantiation, which I seriously doubt) then you may able to get it to work on a different fpga
M
I haven’t used HLS but I guess the code that it emits will be full of references to Xilinx primitives and/or black boxes (propietary IP cores), so trying to port it to even another Xilinx FPGA (not to say a different vendor) will probably be a huge task
K
Is ir possible to copy the generated vhdl code from vivado hls and paste it into quartus to run it over cyclone 4 for example?
I'd rather try to adapt your code to Intel HLS
ZH
I'd rather try to adapt your code to Intel HLS
Is there an Intel hls?!
K
Is there an Intel hls?!
ZH
Thank you
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XC7Z045 is just a SoC with Kintex-7 FPGA
Yeah ryt
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Can we generate picoseconds timer in FPGA by using Resources
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NITHESH
Can we generate picoseconds timer in FPGA by using Resources
Read the datasheet about performance maximums.