Телеграмм чат группы proFpga страница 143

Do you know something how to estimate complexity and approximate number of LUT's that will be used in one always/if/else construction?
(Number of used signals) / (Number of LUT's inputs)
Is that so?

11:53пожаловаться #1

Doka in FPGA technical questions

Aleksandr Kriukov

Do you know something how to estimate complexity and approximate number of LUT's that will be used in one always/if/else construction?
(Number of used signals) / (Number of LUT's inputs)
Is that so?

No way to estimate logic utilization in LUT6/LUT8 era and closed src of HW/synth

11:56пожаловаться #2

Doka in FPGA technical questions

Also we should keep in mind some shit like CARRY8, SLR, DSP48, BRAM, URAM, etc..

11:58пожаловаться #3

If it is about flex10ke?)

12:00пожаловаться #4

2019 June 27

Jesus

One question. How would you generate clock jitter in a testbebch?

no one ?

01:55пожаловаться #5

does anyone here use Spyglass ?

02:07пожаловаться #6

Даня in FPGA technical questions

Jesus

One question. How would you generate clock jitter in a testbebch?

What can be the reason to generate jitter in testbench?

Елисей in FPGA technical questions

09:58пожаловаться #7

Jesus

One question. How would you generate clock jitter in a testbebch?

It seems you need some kind of post-synthesis timing simulation to achieve jitter effects, don't you?

11:29пожаловаться #8

Елисей

It seems you need some kind of post-synthesis timing simulation to achieve jitter effects, don't you?

No. I'm simulating my asic design with clock jitter at pre-synthesis

13:05пожаловаться #9

Diego H in FPGA technical questions

Елисей

It seems you need some kind of post-synthesis timing simulation to achieve jitter effects, don't you?

He's right. Is more useful to run these kind of test after synthesis and not too useful before synthesis. If you run post synthesis, you work with all physical events such as std cell timings, power analysis, etc. If you have a valid concern to simulate jitter before synthesis, then I believe you could play with inter and intra delays in your hdl model first.

17:16пожаловаться #10

2019 June 28

NITHESH in FPGA technical questions

Hello
Has anyone working on AXI interface in Xilinx

17:45пожаловаться #11

NITHESH in FPGA technical questions

Please try to share some documents on AXI

17:45пожаловаться #12

If I want to make delay must i use reset?
1) a_d <= a;
2) a_d <= rst ? 1'b0 : a;

18:06пожаловаться #13

What the best practice tells us?)

18:08пожаловаться #14

Ruslan in FPGA technical questions

Aleksandr Kriukov

If I want to make delay must i use reset?
1) a_d <= a;
2) a_d <= rst ? 1'b0 : a;

Is your logic sync or async? What kind of a delay? Don't get your intention

19:07пожаловаться #15

Ruslan

Is your logic sync or async? What kind of a delay? Don't get your intention

Sync, delay of managing strobe.

19:15пожаловаться #16

Ruslan in FPGA technical questions

Aleksandr Kriukov

Sync, delay of managing strobe.

In most cases simple flip-flop is enough (always @(posedge clk) a_d<= a;) to make a single cycle delay. Adding a reset is design dependant. Take care that reset deasserted synchronously for all parts, that use the same reset signal.

20:24пожаловаться #17

Ruslan

Thanks.

20:26пожаловаться #18

2019 June 29

Read Cummings PDF

12:19пожаловаться #19

2019 July 02

Can anyone provide any documentation for understanding clock jitter? I want to understand how a clock (square wave) is altered by jitter (sine wave)