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FPGA technical questions

2019 June 05

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Andrey S in FPGA technical questions
What do you want to do in LTE context?
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Andrey Shevchenko in FPGA technical questions
If you need to achieve 1ns precision in frame format you don't have to generate 1ns reference clock. You can use a reference comfortable frequency for PL (e.g. 100-200 MHz) but use Farrow filter that does fractional signal upconversion. Control of the  fractional upconversion ratio can provide you as high precesion as you need
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2019 June 06

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Jesus in FPGA technical questions
What's the best way to handle metastability in a serializer ?
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Jesus in FPGA technical questions
I'm building a 22-to-1 parallel to serial converter
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akkyf in FPGA technical questions
2clock fifo
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Ivan in FPGA technical questions
Jesus
What's the best way to handle metastability in a serializer ?
I agree with @akkyf : 2 clokc fifo
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Ivan in FPGA technical questions
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Ivan in FPGA technical questions
I call it Sinchronizer
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Ivan in FPGA technical questions
I've made RS232 controller. Without double satge sinchronizer id didn't work
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Jesus in FPGA technical questions
akkyf
2clock fifo
Imagine you have an input bus of 8 bits.
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Jesus in FPGA technical questions
A fifo is overkill
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Jesus in FPGA technical questions
It es better a simpler solution
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Jesus in FPGA technical questions
I'm reading about creating a valid signal. I mean, a qualifier based synchronizer
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Jesus in FPGA technical questions
Do you have experience with that?
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Jesus in FPGA technical questions
How do you avoid jitter?
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2019 June 07

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Aleksandr Kriukov in FPGA technical questions
Jesus
I'm reading about creating a valid signal. I mean, a qualifier based synchronizer
Please tell about that or give a link.
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2019 June 08

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Jesus in FPGA technical questions
Aleksandr Kriukov
Please tell about that or give a link.
Finally I created my own qualifier based synchronizer
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Jesus in FPGA technical questions
I want to create now a circuit to remove jitter, anyone has experience with this?
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2019 June 09

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Jesus in FPGA technical questions
What techniques to use to attenuate jitter?
Let's talk about jitter attenuator circuits.
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Brian Wu in FPGA technical questions
https://github.com/brianwchh/grassrootsstartup-ComputerVsion-zynq.git  deploy computer vision algorithm on FPGA tutorial
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