CM
Where is the source of Medidor_Interface
Medidor_Interface : https://pastebin.com/2ZnVEaN9
Size: a a a
2019 May 30
EB
I recommend add begin end after else, before if in 14
EB
2) control is 1-bit wire
EB
0 or 1 value, never 2
CM
I recommend add begin end after else, before if in 14
EB
EB
14 - else begin if ..
35 - end
35 - end
EB
begin - end just recommendation. You need change control input port to input [1:0] control
CM
2) control is 1-bit wire
so i must change it to reg [1:0] on Medidor_Function?
EB
input clock, reset_n, enable;
input [1:0] control;CM
input clock, reset_n, enable;
input [1:0] control;thanks a tot <3
I´ll do it
I´ll do it
CM
it works, thanks a lot, god bless u :)
EB
Caíque Moura
it works, thanks a lot, god bless u :)
Pay attention =))
CM
hehehe ;)
D
AS
Yo!
I want to make two modules with other clock whose ratio is a power of two.
If i create slave clock by dividing master clock, do I need to solve metastability problem between two clock domain?
I want to make two modules with other clock whose ratio is a power of two.
If i create slave clock by dividing master clock, do I need to solve metastability problem between two clock domain?
AK
Yo!
I want to make two modules with other clock whose ratio is a power of two.
If i create slave clock by dividing master clock, do I need to solve metastability problem between two clock domain?
I want to make two modules with other clock whose ratio is a power of two.
If i create slave clock by dividing master clock, do I need to solve metastability problem between two clock domain?
The phase of your generated clock will not be the same as master clock, because of clock divider timing paths (wires and logic inside it). So you have to options: synchronize paths from clk1 to clk2, and from clk2 to clk1, or you may leave them asynchronous and use CDC techniques.
N
Hello everyone
N
How will you do 200Mhz to 1picosecond
N
In FPGA