EB
LM_LICENSE_FILE?
Size: a a a
2019 May 25
K
MGLS_LICENSE_FILE
PI
How to check sir is there commands are document guide please share sir
EB
MGLS_LICENSE_FILE
Maybe 😁 LM in modelsim
2019 May 26
BB
Hallo all
2019 May 28
AK
LA
You guys can use the @join_captcha_bot to block such users from joining the chat. It's a CAPTCHA bot.
AS
Hi guys! Try to use enums in quartus and get some troubles.
Have some enum declaration at the top of .sv file
then try to create register of this type
but get an error
Quartus Prime, 18.0.0
Have some enum declaration at the top of .sv file
typedef enum {
FlashStateIdle = 0,
FlashStateCmd,
FlashStateWait
} FlashState;then try to create register of this type
42: reg FlashState state;
43: reg FlashState next_state;
but get an error
Error (10170): Verilog HDL syntax error at spi_flash.sv(42) near text: "state"; expecting ";".
Error (10149): Verilog HDL Declaration error at spi_flash.sv(43): identifier "FlashState" is already declared in the present scope
Quartus Prime, 18.0.0
MI
Hi guys! Try to use enums in quartus and get some troubles.
Have some enum declaration at the top of .sv file
then try to create register of this type
but get an error
Quartus Prime, 18.0.0
Have some enum declaration at the top of .sv file
typedef enum {
FlashStateIdle = 0,
FlashStateCmd,
FlashStateWait
} FlashState;then try to create register of this type
42: reg FlashState state;
43: reg FlashState next_state;
but get an error
Error (10170): Verilog HDL syntax error at spi_flash.sv(42) near text: "state"; expecting ";".
Error (10149): Verilog HDL Declaration error at spi_flash.sv(43): identifier "FlashState" is already declared in the present scope
Quartus Prime, 18.0.0
Why
reg before Flashstate?AS
Why
reg before Flashstate?I think enum is kind of type of bus like
[3:0] for example. I'll try without reg2019 May 29
DH
No, you have a user defined enum of type FlashState. yo have to declare it as a FlasState state, next_state
DH
typedef = user defined. If I do something like
typedef logic [7:0] uint8_tGK
Hi guys! Try to use enums in quartus and get some troubles.
Have some enum declaration at the top of .sv file
then try to create register of this type
but get an error
Quartus Prime, 18.0.0
Have some enum declaration at the top of .sv file
typedef enum {
FlashStateIdle = 0,
FlashStateCmd,
FlashStateWait
} FlashState;then try to create register of this type
42: reg FlashState state;
43: reg FlashState next_state;
but get an error
Error (10170): Verilog HDL syntax error at spi_flash.sv(42) near text: "state"; expecting ";".
Error (10149): Verilog HDL Declaration error at spi_flash.sv(43): identifier "FlashState" is already declared in the present scope
Quartus Prime, 18.0.0
Just FlashState, without reg or wire
DH
My variable is of type uint8_t, not logic [7:0]
AS
thank you, it works
2019 May 30
K
you need to setup license environment variable:
setenv LM_LICENSE_FILE <your license file>
setenv LM_LICENSE_FILE <your license file>
K
also you may update your .bashrc (or .cshrc) with something like:
export LM_LICENSE_FILE = <path to your license.dat file>
export MGLS_LICENSE_FILE = <path to your license.dat file>
export PATH = $PATH:<path to modelsim executable>
export LM_LICENSE_FILE = <path to your license.dat file>
export MGLS_LICENSE_FILE = <path to your license.dat file>
export PATH = $PATH:<path to modelsim executable>
CM
hi every one, I have a doubt, my
Medidor_Function does not work, it does not go to 52. the control´s signal rise just once, how can I solve it, I have no idea😁, I just starting using verilog. Here is the Medidor_Function code: https://pastebin.com/j4r1TCw6
and the test bench is here: https://pastebin.com/gJ7ZVM6T
here is the modelSim simulation of signals
Medidor_Function does not work, it does not go to 52. the control´s signal rise just once, how can I solve it, I have no idea😁, I just starting using verilog. Here is the Medidor_Function code: https://pastebin.com/j4r1TCw6
and the test bench is here: https://pastebin.com/gJ7ZVM6T
here is the modelSim simulation of signals
CM
EB
Caíque Moura
hi every one, I have a doubt, my
Medidor_Function does not work, it does not go to 52. the control´s signal rise just once, how can I solve it, I have no idea😁, I just starting using verilog. Here is the Medidor_Function code: https://pastebin.com/j4r1TCw6
and the test bench is here: https://pastebin.com/gJ7ZVM6T
here is the modelSim simulation of signals
Medidor_Function does not work, it does not go to 52. the control´s signal rise just once, how can I solve it, I have no idea😁, I just starting using verilog. Here is the Medidor_Function code: https://pastebin.com/j4r1TCw6
and the test bench is here: https://pastebin.com/gJ7ZVM6T
here is the modelSim simulation of signals
Where is the source of Medidor_Interface