Yeah thanks for this.I wanted to practice verification part as well.So if you can guide me on this as well.

Hi, everybody. Could you say, what last vesion of quartus support FLEX10KE FPGAs.

9.1 if I'm not mistaken

Thank you!

Hello. Could somebody help me with UART in VHDL?

Hi i have a question..



You have a I2C master in your device and communicating with a slave of temperature sensor.

Since you are master, you are doing some read operation and at the middle your FPGA alone restarted.

What will happen to the I2C communication channel ?

If this will cause the issue, how to resolve this..?

Note : chip dont have hard reset

Hi,

This looks be I2C lockup condition.

If there is no hard reset for slave, check does it have I2C timeout period. If timeout is available on slave , then lockup condition won't occur.

Other way to handle this condition would be to monitor the bus busy and generate a Plus one clock to actual count to get the bus released by slave

Hope this helps

Let

Thanks 😊

Let me know Anybody used intel quartus prime pro...

I have some doubts regarding the PC performance while running the tool..?

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Hi guys, i am a bit new to the world of fpga and i need a couple of advices. let' assume that we have 4 CCD image sensors and i want create one image and transfer it to a conputer

My idea was to use 4 fifo to temporary store the pixels coming from the 4 cmos

Than use a state machine to empy the fifo an populate a RAM

That represents my image

And then another state machine to stream sequentially  all the pixels to the computer

Is It the correct way to implement It?

I mind your question is about system approach but not about fpga