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FPGA technical questions

381 membersпожаловаться на группу
2019 October 19

AK

Andrew Kushchenko in FPGA technical questions
Sometimes signals are red, but signaltap works correctly. Did you tried run this?
As another solution you can try add theses signals again. Maybe changed toplevel name or something in the hierarchy
источник
23:22пожаловаться#1

RB

Roman Belenkov in FPGA technical questions
I tried to run. All signals are stupidly drawn to zeros. Even reset_n, which was 100% set to one.
источник
23:45пожаловаться#2

AK

Andrew Kushchenko in FPGA technical questions
Try setup your signaltap again
источник
23:54пожаловаться#3
2019 October 20

P

P in FPGA technical questions
try to clear db dir and rebuild )
источник
08:38пожаловаться#4

Д

Даня in FPGA technical questions
Roman Belenkov
There no instance in your signal name, are you sure you’re adding them properly?
источник
10:49пожаловаться#5
2019 October 22

ZK

Zaid Khan in FPGA technical questions
Can anyone here please suggest me a theory oriented book of system verilog
источник
17:31пожаловаться#6

ZK

Zaid Khan in FPGA technical questions
Or notes
источник
17:31пожаловаться#7

K

Kostya Goodsoul in FPGA technical questions
pure theory: https://standards.ieee.org/standard/1800-2017.html
standards.ieee.org
1800-2017 - IEEE Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification
Language
The definition of the language syntax and semantics for SystemVerilog, which is a unified hardware design, specification, and verification language, is provided. This standard includes support for modeling hardware at the behavioral, register transfer level (RTL), and gate-level abstraction levels, and for writing testbenches using coverage, assertions, object-oriented programming, and constrained random verification. The standard also provides application programming interfaces (APIs) to foreign programming languages. (The PDF of this standard is available at no cost at https://ieeexplore.ieee.org/browse/standards/get-program/page compliments of Accellera Systems Initiative)
источник
17:33пожаловаться#8

ZK

Zaid Khan in FPGA technical questions
Bro I can't see it can you please download and send it here
источник
17:36пожаловаться#9

ZK

Zaid Khan in FPGA technical questions
If not a problem
источник
17:36пожаловаться#10

S9

Srinivasan 97 in FPGA technical questions
Anyone knows how to design LPF filter in verilog
источник
17:39пожаловаться#11

K

Konstantin in FPGA technical questions
Zaid Khan
If not a problem
https://www.google.com/search?client=ms-android-samsung-gj-rev1&sxsrf=ACYBGNRtTeFJdiX5O_cr3a9LNf3Yx-KMDQ%3A1571755110085&ei=ZhSvXe3VBKKorgS76Im4Dg&q=ieee+1800+2017+pdf&oq=ieee+1800+2017+pdf&gs_l=mobile-gws-wiz-serp.12..33i22i29i30.3198.5518..7104...0.0..0.211.548.0j3j1......0....1.Kcg8t0YSjOU

Click the very first link and you will get pdf. Welcome  to World Wide Web, let me your guide here
Google
ieee 1800 2017 pdf - Google Search
источник
17:39пожаловаться#12

K

Konstantin in FPGA technical questions
IEEE_Std1800-2017_8299595.pdf
(15.3 Мб)
IEEE_Std1800-2017_8299595.pdf
источник
17:41пожаловаться#13

K

Konstantin in FPGA technical questions
Srinivasan 97
Anyone knows how to design LPF filter in verilog
- use verilog to write fir filter
-use matlab or python to calculate filter coefficients
источник
17:42пожаловаться#14

S9

Srinivasan 97 in FPGA technical questions
Konstantin
- use verilog to write fir filter
-use matlab or python to calculate filter coefficients
Can you please suggest any design documents
источник
17:43пожаловаться#15

K

Konstantin in FPGA technical questions
Srinivasan 97
Can you please suggest any design documents
https://zipcpu.com/dsp/2017/09/15/fastfir.html
Zipcpu
Building a high speed Finite Impulse Response (FIR) Digital Filter
Some time ago, an individual posted on Digilent’sforum that he wasn’t able to getXilinx’sFinite Impulse Response (FIR)filtercompilergenerated code to work.  ...
источник
17:54пожаловаться#16

S9

Srinivasan 97 in FPGA technical questions
Thank you
источник
17:54пожаловаться#17

RB

Roman Belenkov in FPGA technical questions
Comrades, I solved the problem. Installed quartus 19.1, the signals also remained red, but they now work as they should. Thank!!!
источник
18:31пожаловаться#18
2019 October 24

EB

Evgeniy Bolnov in FPGA technical questions
Srinivasan 97
Anyone knows how to design LPF filter in verilog
site for calc coeff http://t-filter.engineerjs.com/
Engineerjs
TFilter - Free online FIR filter design
Free online FIR filter design application
источник
09:47пожаловаться#19
2019 October 25

J

Jesus in FPGA technical questions
Is anyone here working in the USA?
источник
22:18пожаловаться#20