J
Proficiency with Verilog RTL coding (LEC, CDC, DFT)
Size: a a a
2019 September 19
J
What is LEC ?
K
What is LEC ?
Logic Equivalence Checker.
Please, use the single message for the question, not the chain of small ones.
Please, use the single message for the question, not the chain of small ones.
LI
in which software do you use that constraint ?
Vivado
RB
thank!
2019 September 23
dl
Hey guys! If anyone did high - speed ethernet, please tell me how long the difference pair should be between the fpga and qsfp 28gbps transceiver?
2019 September 26
AE
Hi I want to do sinusoidal by using zedboard could any one help me PLZ. I find papers took about DDS by using Soc. However I don't know how to do it.
J
Abdalwahab Essa
Hi I want to do sinusoidal by using zedboard could any one help me PLZ. I find papers took about DDS by using Soc. However I don't know how to do it.
You can use DPI
J
Create a Sine Wave Generator Using SystemVerilog - Functional Verification - Cadence Blogs - Cadence Community
https://community.cadence.com/cadence_blogs_8/b/fv/posts/create-a-sine-wave-generator-using-systemverilog
https://community.cadence.com/cadence_blogs_8/b/fv/posts/create-a-sine-wave-generator-using-systemverilog
2019 September 27
AE
That Good thank you ...Actually I want to do that by DDS just simple one
R
Abdalwahab Essa
Hi I want to do sinusoidal by using zedboard could any one help me PLZ. I find papers took about DDS by using Soc. However I don't know how to do it.
In a few words it would be like: create a block design with zynq PM, add DDS IPcore from library and set its parameters, connect inputs to zynq bus (some of the AXI kind, I suppose) and outputs to pins. Also, when generating IP core for DDS there could be an option to generate example design that you can refer to.
2019 September 28
AE
Thank you sir for helping. I hope if you have an example using vivado.
R
Abdalwahab Essa
Thank you sir for helping. I hope if you have an example using vivado.
Google for zynq book user guide, there are plenty of examples. Also, this guide targets zed board
AE
Google for zynq book user guide, there are plenty of examples. Also, this guide targets zed board
Okay sir thank you . I will try 👍
2019 September 30
J
which IDEs do you use? (apart from the Xilinx/Altera ones)
Д
VScode
EB
which IDEs do you use? (apart from the Xilinx/Altera ones)
sublime + plugins
K
sublime + plugins
Same thing
EB
what do you think about this one ? https://github.com/rochus-keller/QtcVerilog/blob/master/README.md
looks interesting, but what about linter