C
Is there someone that uses ghdl and gtkwave for simulation? I need some hint to improve my Makefile
You can try: https://github.com/TerosTechnology/terosHDL
Size: a a a
2019 October 05
2019 October 06
QL
I saw the teros presentation at the ORCONF this year, i have benn using that IDE for a year in my company and my team is amazed
A
Uhm, now I'm using vim with a Makefile
A
It does the job
A
Btw is there a VHDL to schematic (image) converter free?
A
I see that yosys do it but in verilog
2019 October 10
PI
How to run batch mode ( .do file) in windows cmd prompt
PI
For Questasim tool
AK
Prince😊 Ind
For Questasim tool
From questasim console
AG
vsim -c -do file.do
2019 October 12
J
I'm a bit confused with "program" block in SystemVerilog. When do you use it? for what it's worth?
MK
J
What does "race-free" mean?
K
What does "race-free" mean?
It is when you have delta cycle (or just tiny) delay between your signals
MK
What does "race-free" mean?
Run an example and look at addr behavior
2019 October 16
Д
Hello everybody, how do you obfuscate/encrypt hdl-code so it hard to reverse engineer?
2019 October 17
M
I recently started learning zigbee, but i couldnt understand it clearly, can anyone help me out
K
Hello everybody, how do you obfuscate/encrypt hdl-code so it hard to reverse engineer?
What exactly do you mean?
- You can encrypt fpga bitstream
- Encrypt IP core
- obfuscate rtl code itself
- You can encrypt fpga bitstream
- Encrypt IP core
- obfuscate rtl code itself