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118 votes is too small amount
Size: a a a
2019 August 07
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Which is more preferred verilog or VHDL?
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118 votes is too small amount
small for which purposes?
I'm afraid to ask: you scientist?
I'm afraid to ask: you scientist?
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small for which purposes?
I'm afraid to ask: you scientist?
I'm afraid to ask: you scientist?
For independent conclusions
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small for which purposes?
I'm afraid to ask: you scientist?
I'm afraid to ask: you scientist?
Not yet, just a student
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For independent conclusions
independent from what?
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From limitations of selections: who a this 118 people, what kind of vendor do they use, may be they all work in one company etc.
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Btw where is SV
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Ok. I see.
Please stay in context: guy ask that community ~300 members
Please stay in context: guy ask that community ~300 members
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Btw where is SV
dont know what is SV. Probably Silicon Valley? 🤔
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Ok. I see.
Please stay in context: guy ask that community ~300 members
Please stay in context: guy ask that community ~300 members
That’s why my answer tells him that his question is not a good idea
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dont know what is SV. Probably Silicon Valley? 🤔
I think - system verilog )
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I think - system verilog )
Oh... I forgot for that verification sh!t 😂
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unfortunately @Blackmagic_b dont specify terget: RTL/verif 🤷♂️
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Unfortunately, SV can be used in rtl 🤓
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How about AHDL
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Unfortunately, SV can be used in rtl 🤓
good luck! 😬
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Thank you ☺️
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How about AHDL
how about schematic entry?