Д
I heard that schematic more for teaching purposes, but some people use it mixing with hdl blocks
Size: a a a
2019 August 07
AK
how about schematic entry?
Do you know why I really hate FPGAs? Because I can not use my spice netlists in it! It is ridiculous!
DG
Oh... I forgot for that verification sh!t 😂
3) Use respectful communication. Remember that you are among professional engineers.
DG
And we finish holywar discussion.
D
3) Use respectful communication. Remember that you are among professional engineers.
Take it easy! It's just joke!
2019 August 11
A
how about schematic entry?
🙈
2019 August 12
F
Hi. A very basic Verilog question that I can't seem to figure out:
always @ (posedge Clk) begin
A <= 1'b0;
B <= A;
end
What would the value of B be after a single clock posedge?
always @ (posedge Clk) begin
A <= 1'b0;
B <= A;
end
What would the value of B be after a single clock posedge?
AB
Hi. A very basic Verilog question that I can't seem to figure out:
always @ (posedge Clk) begin
A <= 1'b0;
B <= A;
end
What would the value of B be after a single clock posedge?
always @ (posedge Clk) begin
A <= 1'b0;
B <= A;
end
What would the value of B be after a single clock posedge?
X
J
Hi. A very basic Verilog question that I can't seem to figure out:
always @ (posedge Clk) begin
A <= 1'b0;
B <= A;
end
What would the value of B be after a single clock posedge?
always @ (posedge Clk) begin
A <= 1'b0;
B <= A;
end
What would the value of B be after a single clock posedge?
X
J
Hi. A very basic Verilog question that I can't seem to figure out:
always @ (posedge Clk) begin
A <= 1'b0;
B <= A;
end
What would the value of B be after a single clock posedge?
always @ (posedge Clk) begin
A <= 1'b0;
B <= A;
end
What would the value of B be after a single clock posedge?
That's like a pipeline. And you should use a reset signal to initialize all your registers
F
So in the second cycle it would become 1'b0, right?
J
So in the second cycle it would become 1'b0, right?
Yes. You should simulate it, and see the behavior by yourself
F
Thanks. I am trying to "reverse-engineer" some Verilog code, and I was wondering whether that would be the case, or why else one would need two different registers with the same value in them.
J
Thanks. I am trying to "reverse-engineer" some Verilog code, and I was wondering whether that would be the case, or why else one would need two different registers with the same value in them.
Learn about pipeline technique, because the code you are studying it's a pipeline
F
I have another question. In the verilog file this appears:
F
MdcEn_n is not mentioned anywhere else in the file. How can this piece of code be valid, if MdcEn_n is not defined in the module?
J
MdcEn_n is not mentioned anywhere else in the file. How can this piece of code be valid, if MdcEn_n is not defined in the module?
Can you share the code?
RY
MdcEn_n is not mentioned anywhere else in the file. How can this piece of code be valid, if MdcEn_n is not defined in the module?
This is a strange verilog feature. It is possible to use 1bit wire without its definition