J
What do you do to tolerate jitter in your synchronizer circuits?
Size: a a a
2019 July 11
2019 July 13
J
Hi, I have a design (a serializer) with two input clocks and one input reset. I just synchronized the reset on both clock domains but I did not thought in the reset order, I mean, in case of reset activation, do I have to activate first the reset for the slow clock and then the other one? I don't know much about this topic, so any help is more than welcome
J
I have another question. There are golden rules for this kind of designs, like: the first and last thing to to in the design is to register the data. But there are exceptions, where the last stage should not be the data registration of the outcoming data. What are those exceptions ?
Н
Hi, I have a design (a serializer) with two input clocks and one input reset. I just synchronized the reset on both clock domains but I did not thought in the reset order, I mean, in case of reset activation, do I have to activate first the reset for the slow clock and then the other one? I don't know much about this topic, so any help is more than welcome
maybe you should use the same asynchronous reset (a reset will occur for two clock domains from one asynchronous reset signal) for fast and slow clocks?
I could be wrong
I could be wrong
J
maybe you should use the same asynchronous reset (a reset will occur for two clock domains from one asynchronous reset signal) for fast and slow clocks?
I could be wrong
I could be wrong
No. You can't do that
2019 July 15
Б
Hi! Does anyone know an open source rtl code formatter/beautifier? Like clang-format for C/C++, but for Verilog/System Verilog.
D
Hi! Does anyone know an open source rtl code formatter/beautifier? Like clang-format for C/C++, but for Verilog/System Verilog.
I'm also wanna to know tool name to convert legacy code.
Let me know if you find solution
Let me know if you find solution
J
Hi! Does anyone know an open source rtl code formatter/beautifier? Like clang-format for C/C++, but for Verilog/System Verilog.
Edaplayground
2019 July 17
AE
Fpga 4 fun
2019 July 24
I
Hi! Does anyone know an open source rtl code formatter/beautifier? Like clang-format for C/C++, but for Verilog/System Verilog.
I use Aldec hdl
I
I don't really want to use a FIFO
Make fifo of one-step depth
J
Does anyone here use VCS?
J
Indexed part-select and bit replication are not working for me
I
Vcs == visual c studio?
MT
Vcs == visual c studio?
In the context of this group VCS is the functional simulation solution from Synopsys 😁
J
Vcs == visual c studio?
No, I'm refering to Synopsys VCS
R
Does anyone here use VCS?
I'm using it, mostly for verification with systemverilog. Do not have issues with replication ( {,} right?), nor with indexed part select.
P
Anyone need fpga got a lot in stock
J
I'm using it, mostly for verification with systemverilog. Do not have issues with replication ( {,} right?), nor with indexed part select.
Did you use any option to indicate you are using Verilog 2001?