Н
Hello colleagues. Please, tell me a good guide ( level of circuitry of the board and RTL) for debugging the FPGA (Artix 7 xca35t) and DDR3 (Micron MT41K128M16) systems.
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2019 July 05
D
Hello colleagues. Please, tell me a good guide ( level of circuitry of the board and RTL) for debugging the FPGA (Artix 7 xca35t) and DDR3 (Micron MT41K128M16) systems.
ILA? 🤔
Н
ILA? 🤔
thx
AK
NITHESH
Any one has PDF on AXI 4
Really?
https://bit.ly/2Yucrap
https://bit.ly/2Yucrap
2019 July 07
AE
Hi I have a question? I want to generate 11 ghz by using zedboard with fmc I hope if anybody have idea to help or advise me.
D
Abdalwahab Essa
Hi I have a question? I want to generate 11 ghz by using zedboard with fmc I hope if anybody have idea to help or advise me.
Use MGTs. They have connect to FMC
2019 July 08
AE
Use MGTs. They have connect to FMC
Thank you so much to your advice
DF
hi all!! did you ever configure the Si5324 on the VC709 for a working frequency of 125MHz?
Е
w/o to, just
std_logic()?Е
Drug Fyuvdr
hi all!! did you ever configure the Si5324 on the VC709 for a working frequency of 125MHz?
2019 July 09
PI
w/o to, just
std_logic()?Thank you for the response sir
2019 July 10
J
Imagine you have a 10 bits data bus, and its clock. Each clock cycle, new 10 bits enter in your system. What's the best moment to sample the data? Data clock is 20 times slower than system clock. That is, in one clock cycle of the data clock, we have 20 cycles of the system clock
J
They are asynchronous clocks
НН
if you can to read this so precisionly in 19 tick of sysclk then read it in 19 systick after new async clock tick. If you have a jitter, than better to read it in middle between async ticks, in your case it is in 10 systick. IMHO
R
They are asynchronous clocks
Load data to the async FIFO to manage CDC. So you will write on rising edge of data bus and start reading on sysclk when FIFO not empty
J
Load data to the async FIFO to manage CDC. So you will write on rising edge of data bus and start reading on sysclk when FIFO not empty
I don't really want to use a FIFO
D
in any incomprehensible case use FIFO 🤪
S
in any incomprehensible case use FIFO 🤪
🤙🏾
J
in any incomprehensible case use FIFO 🤪
That would be a bit overkill for this small serializer
D
That would be a bit overkill for this small serializer
just pick up larger FPGA 😂😂😂