the code:
ficaria assim?
module Medidor_Function (clock, reset_n, enable, control, data_out, data_in);
input clock, reset_n, control, enable;
output reg [0:31] data_out;
input [31:0] data_in;
integer flag;
always @(negedge clock)
begin
if(!reset_n)
data_out <= 0;
flag <=1;
else
if (enable)
data_out <= data_out + data_in;
flag <=1;
end
else
flag<=0;
endmodule