A
Okay 👍
Size: a a a
2019 April 22
AS
because you have different clocks etc.
J
Amit
I tried two then three flipflop logic but result is same.
double flopping technique is only for single bit signals. You have a bus there.
ΔΒ
double flopping technique is only for single bit signals. You have a bus there.
and for Gray counters too, if they count +-1 at a time
A
and for Gray counters too, if they count +-1 at a time
++
J
and for Gray counters too, if they count +-1 at a time
so, if you have an 8 bit gray counter, you will put two flip-flops for each line of data (that is 16 flip-flops), right ?
ΔΒ
J
thanks
AS
so, if you have an 8 bit gray counter, you will put two flip-flops for each line of data (that is 16 flip-flops), right ?
You can look through that Sunburst tutorials for elaboration on this Gray counters topic.
http://www.sunburst-design.com/papers/CummingsSNUG2008Boston_CDC.pdf
http://www.sunburst-design.com/papers/CummingsSNUG2002SJ_FIFO1.pdf
http://www.sunburst-design.com/papers/CummingsSNUG2008Boston_CDC.pdf
http://www.sunburst-design.com/papers/CummingsSNUG2002SJ_FIFO1.pdf
2019 April 25
A
Hello. I have a very old FPGA design for XC4000 in Xilinx Foundation
Is there any easy way to migrate sources (schematic entry) to Vivado (newer FPGA of course)?
Is there any easy way to migrate sources (schematic entry) to Vivado (newer FPGA of course)?
D
Hello. I have a very old FPGA design for XC4000 in Xilinx Foundation
Is there any easy way to migrate sources (schematic entry) to Vivado (newer FPGA of course)?
Is there any easy way to migrate sources (schematic entry) to Vivado (newer FPGA of course)?
Very easy way: hire cheap contractor (e.g. students) to manual convertations.
Keep in mind xc4000 not so huge in comparison w/ US+ family
Keep in mind xc4000 not so huge in comparison w/ US+ family
A
We also tried to convert edif to verilog (wrote a program) but there were some problems with signal naming.
2019 April 26
J
does anyone know a good tutorial to implement a Risc-V softcore in a Xilinx FPGA ?
LA
does anyone know a good tutorial to implement a Risc-V softcore in a Xilinx FPGA ?
The computer organization and design from Patterson & Hennessy RISC-V edition has several tips, but nothing specific to Xilinx. It's not really on tutorial format. There is an extra section freely available online with a tutorial for Verilog and VHDL:
* https://www.elsevier.com/__data/assets/pdf_file/0010/297514/Section-4-13_Advanced.pdf#Section%204.13
* https://www.elsevier.com/books-and-journals/book-companion/9780128122754/tutorials#Tutorials
* https://www.elsevier.com/__data/assets/pdf_file/0010/297514/Section-4-13_Advanced.pdf#Section%204.13
* https://www.elsevier.com/books-and-journals/book-companion/9780128122754/tutorials#Tutorials
LA
The other book from same authors is still further oriented to hardware and also has been converted to RISC-V if I recall correctly (still not on a tutorial shape, but bookish)
2019 April 30
PI
Please help me how the denominator become zero here thank you
a
i think if b=4'b1111;
PI
But they given is not 0 during the assignment to foo
a
Verilog standard defines division by zero as returning X